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-rw-r--r--src/wld/intel/batch.c126
-rw-r--r--src/wld/intel/batch.h88
-rw-r--r--src/wld/intel/blt.h549
-rw-r--r--src/wld/intel/i965_pci_ids.h137
-rw-r--r--src/wld/intel/intel.c358
-rw-r--r--src/wld/intel/mi.h27
6 files changed, 570 insertions, 715 deletions
diff --git a/src/wld/intel/batch.c b/src/wld/intel/batch.c
index ce15ef1..2618a4a 100644
--- a/src/wld/intel/batch.c
+++ b/src/wld/intel/batch.c
@@ -27,69 +27,97 @@
#include <i915_drm.h>
#include <stdlib.h>
-static const struct intel_device_info device_info_i965 = {.gen = 4};
-static const struct intel_device_info device_info_g4x = {.gen = 4};
-static const struct intel_device_info device_info_ilk = {.gen = 5};
-static const struct intel_device_info device_info_snb_gt1 = {.gen = 6};
-static const struct intel_device_info device_info_snb_gt2 = {.gen = 6};
-static const struct intel_device_info device_info_ivb_gt1 = {.gen = 7};
-static const struct intel_device_info device_info_ivb_gt2 = {.gen = 7};
-static const struct intel_device_info device_info_byt = {.gen = 7};
-static const struct intel_device_info device_info_hsw_gt1 = {.gen = 7};
-static const struct intel_device_info device_info_hsw_gt2 = {.gen = 7};
-static const struct intel_device_info device_info_hsw_gt3 = {.gen = 7};
-
-static const struct intel_device_info *device_info(int device_id) {
- switch (device_id) {
-#define CHIPSET(device_id, type, name) \
- case device_id: \
- return &device_info_##type;
+static const struct intel_device_info device_info_i965 = { .gen = 4 };
+static const struct intel_device_info device_info_g4x = { .gen = 4 };
+static const struct intel_device_info device_info_ilk = { .gen = 5 };
+static const struct intel_device_info device_info_snb_gt1 = { .gen = 6 };
+static const struct intel_device_info device_info_snb_gt2 = { .gen = 6 };
+static const struct intel_device_info device_info_ivb_gt1 = { .gen = 7 };
+static const struct intel_device_info device_info_ivb_gt2 = { .gen = 7 };
+static const struct intel_device_info device_info_byt = { .gen = 7 };
+static const struct intel_device_info device_info_hsw_gt1 = { .gen = 7 };
+static const struct intel_device_info device_info_hsw_gt2 = { .gen = 7 };
+static const struct intel_device_info device_info_hsw_gt3 = { .gen = 7 };
+static const struct intel_device_info device_info_bdw_gt1 = { .gen = 8 };
+static const struct intel_device_info device_info_bdw_gt2 = { .gen = 8 };
+static const struct intel_device_info device_info_bdw_gt3 = { .gen = 8 };
+static const struct intel_device_info device_info_chv = { .gen = 8 };
+static const struct intel_device_info device_info_skl_gt1 = { .gen = 9 };
+static const struct intel_device_info device_info_skl_gt2 = { .gen = 9 };
+static const struct intel_device_info device_info_skl_gt3 = { .gen = 9 };
+static const struct intel_device_info device_info_skl_gt4 = { .gen = 9 };
+static const struct intel_device_info device_info_bxt = { .gen = 9 };
+static const struct intel_device_info device_info_bxt_2x6 = { .gen = 9 };
+static const struct intel_device_info device_info_kbl_gt1 = { .gen = 9 };
+static const struct intel_device_info device_info_kbl_gt1_5 = { .gen = 9 };
+static const struct intel_device_info device_info_kbl_gt2 = { .gen = 9 };
+static const struct intel_device_info device_info_kbl_gt3 = { .gen = 9 };
+static const struct intel_device_info device_info_kbl_gt4 = { .gen = 9 };
+static const struct intel_device_info device_info_glk = { .gen = 9 };
+static const struct intel_device_info device_info_glk_2x6 = { .gen = 9 };
+static const struct intel_device_info device_info_cfl_gt1 = { .gen = 9 };
+static const struct intel_device_info device_info_cfl_gt2 = { .gen = 9 };
+static const struct intel_device_info device_info_cfl_gt3 = { .gen = 9 };
+static const struct intel_device_info device_info_cnl_2x8 = { .gen = 10 };
+static const struct intel_device_info device_info_cnl_3x8 = { .gen = 10 };
+static const struct intel_device_info device_info_cnl_4x8 = { .gen = 10 };
+static const struct intel_device_info device_info_cnl_5x8 = { .gen = 10 };
+
+static const struct intel_device_info * device_info(int device_id)
+{
+ switch (device_id)
+ {
+#define CHIPSET(device_id, type, name) \
+ case device_id: return &device_info_ ## type;
#include "i965_pci_ids.h"
#undef CHIPSET
- default:
- return NULL;
- }
+ default: return NULL;
+ }
}
-bool intel_batch_initialize(struct intel_batch *batch,
- drm_intel_bufmgr *bufmgr) {
- int device_id = drm_intel_bufmgr_gem_get_devid(bufmgr);
+bool intel_batch_initialize(struct intel_batch * batch,
+ drm_intel_bufmgr * bufmgr)
+{
+ int device_id = drm_intel_bufmgr_gem_get_devid(bufmgr);
- batch->command_count = 0;
- batch->device_info = device_info(device_id);
+ batch->command_count = 0;
+ batch->device_info = device_info(device_id);
- if (!batch->device_info)
- return false;
+ if (!batch->device_info)
+ return false;
- /* Alignment argument (4096) is not used */
- batch->bo =
- drm_intel_bo_alloc(bufmgr, "batchbuffer", sizeof batch->commands, 4096);
+ /* Alignment argument (4096) is not used */
+ batch->bo = drm_intel_bo_alloc(bufmgr, "batchbuffer",
+ sizeof batch->commands, 4096);
- if (!batch->bo)
- return false;
+ if (!batch->bo)
+ return false;
- return true;
+ return true;
}
-void intel_batch_finalize(struct intel_batch *batch) {
- drm_intel_bo_unreference(batch->bo);
+void intel_batch_finalize(struct intel_batch * batch)
+{
+ drm_intel_bo_unreference(batch->bo);
}
-void intel_batch_flush(struct intel_batch *batch) {
- if (batch->command_count == 0)
- return;
+void intel_batch_flush(struct intel_batch * batch)
+{
+ if (batch->command_count == 0)
+ return;
- intel_batch_add_dword(batch, MI_BATCH_BUFFER_END);
+ intel_batch_add_dword(batch, MI_BATCH_BUFFER_END);
- /* Pad the batch buffer to the next quad-word. */
- if (batch->command_count & 1)
- intel_batch_add_dword(batch, MI_NOOP);
+ /* Pad the batch buffer to the next quad-word. */
+ if (batch->command_count & 1)
+ intel_batch_add_dword(batch, MI_NOOP);
- drm_intel_bo_subdata(batch->bo, 0, batch->command_count << 2,
- batch->commands);
- drm_intel_bo_mrb_exec(batch->bo, batch->command_count << 2, NULL, 0, 0,
- batch->device_info->gen >= 6 ? I915_EXEC_BLT
- : I915_EXEC_DEFAULT);
- drm_intel_gem_bo_clear_relocs(batch->bo, 0);
- batch->command_count = 0;
+ drm_intel_bo_subdata(batch->bo, 0, batch->command_count << 2,
+ batch->commands);
+ drm_intel_bo_mrb_exec(batch->bo, batch->command_count << 2, NULL, 0, 0,
+ GEN(batch, 6) ? I915_EXEC_BLT
+ : I915_EXEC_DEFAULT);
+ drm_intel_gem_bo_clear_relocs(batch->bo, 0);
+ batch->command_count = 0;
}
+
diff --git a/src/wld/intel/batch.h b/src/wld/intel/batch.h
index 682b41c..cc9d1d9 100644
--- a/src/wld/intel/batch.h
+++ b/src/wld/intel/batch.h
@@ -24,69 +24,83 @@
#ifndef WLD_INTEL_BATCH_H
#define WLD_INTEL_BATCH_H
-#include <intel_bufmgr.h>
#include <stdarg.h>
#include <stdbool.h>
#include <stdint.h>
+#include <intel_bufmgr.h>
#define INTEL_BATCH_MAX_COMMANDS (1 << 13)
#define INTEL_BATCH_RESERVED_COMMANDS 2
#define INTEL_BATCH_SIZE (INTEL_BATCH_MAX_COMMANDS << 2)
-enum intel_batch_result { INTEL_BATCH_SUCCESS, INTEL_BATCH_NO_SPACE };
+enum intel_batch_result
+{
+ INTEL_BATCH_SUCCESS,
+ INTEL_BATCH_NO_SPACE
+};
-struct intel_device_info {
- int gen;
+struct intel_device_info
+{
+ int gen;
};
-struct intel_batch {
- const struct intel_device_info *device_info;
- drm_intel_bo *bo;
- uint32_t commands[INTEL_BATCH_MAX_COMMANDS];
- uint32_t command_count;
+#define GEN(b, m) ((b)->device_info->gen >= (m))
+
+struct intel_batch
+{
+ const struct intel_device_info * device_info;
+ drm_intel_bo * bo;
+ uint32_t commands[INTEL_BATCH_MAX_COMMANDS];
+ uint32_t command_count;
};
-bool intel_batch_initialize(struct intel_batch *batch,
- drm_intel_bufmgr *bufmgr);
+bool intel_batch_initialize(struct intel_batch * batch,
+ drm_intel_bufmgr * bufmgr);
-void intel_batch_finalize(struct intel_batch *batch);
+void intel_batch_finalize(struct intel_batch * batch);
-void intel_batch_flush(struct intel_batch *batch);
+void intel_batch_flush(struct intel_batch * batch);
-static inline uint32_t intel_batch_check_space(struct intel_batch *batch,
- uint32_t size) {
- return (INTEL_BATCH_MAX_COMMANDS - INTEL_BATCH_RESERVED_COMMANDS -
- batch->command_count) >= size;
+static inline uint32_t intel_batch_check_space(struct intel_batch * batch,
+ uint32_t size)
+{
+ return (INTEL_BATCH_MAX_COMMANDS - INTEL_BATCH_RESERVED_COMMANDS
+ - batch->command_count) >= size;
}
-static inline void intel_batch_ensure_space(struct intel_batch *batch,
- uint32_t size) {
- if (!intel_batch_check_space(batch, size))
- intel_batch_flush(batch);
+static inline void intel_batch_ensure_space(struct intel_batch * batch, uint32_t size)
+{
+ if (!intel_batch_check_space(batch, size))
+ intel_batch_flush(batch);
}
-static inline void intel_batch_add_dword(struct intel_batch *batch,
- uint32_t dword) {
- batch->commands[batch->command_count++] = dword;
+static inline void intel_batch_add_dword(struct intel_batch * batch,
+ uint32_t dword)
+{
+ batch->commands[batch->command_count++] = dword;
}
-static inline void intel_batch_add_dwords_va(struct intel_batch *batch,
- uint32_t count, va_list dwords) {
- while (count--)
- intel_batch_add_dword(batch, va_arg(dwords, uint32_t));
+static inline void intel_batch_add_dwords_va(struct intel_batch * batch,
+ uint32_t count, va_list dwords)
+{
+ while (count--)
+ intel_batch_add_dword(batch, va_arg(dwords, uint32_t));
}
-static inline void intel_batch_add_dwords(struct intel_batch *batch,
- uint32_t count, ...) {
- va_list dwords;
- va_start(dwords, count);
- intel_batch_add_dwords_va(batch, count, dwords);
- va_end(dwords);
+static inline void intel_batch_add_dwords(struct intel_batch * batch,
+ uint32_t count, ...)
+{
+ va_list dwords;
+ va_start(dwords, count);
+ intel_batch_add_dwords_va(batch, count, dwords);
+ va_end(dwords);
}
-static inline uint32_t intel_batch_offset(struct intel_batch *batch,
- uint32_t command_index) {
- return (batch->command_count + command_index) << 2;
+static inline uint32_t intel_batch_offset(struct intel_batch * batch,
+ uint32_t command_index)
+{
+ return (batch->command_count + command_index) << 2;
}
#endif
+
diff --git a/src/wld/intel/blt.h b/src/wld/intel/blt.h
index 41670d2..0d9486b 100644
--- a/src/wld/intel/blt.h
+++ b/src/wld/intel/blt.h
@@ -29,287 +29,360 @@
#define INTEL_CLIENT_BLT 0x2
-enum blt_op {
- BLT_OP_XY_SETUP_BLT = 0x01,
- BLT_OP_XY_TEXT_BLT = 0x26,
- BLT_OP_XY_TEXT_IMMEDIATE_BLT = 0x31,
- BLT_OP_XY_COLOR_BLT = 0x50,
- BLT_OP_XY_SRC_COPY_BLT = 0x53
+enum blt_op
+{
+ BLT_OP_XY_SETUP_BLT = 0x01,
+ BLT_OP_XY_TEXT_BLT = 0x26,
+ BLT_OP_XY_TEXT_IMMEDIATE_BLT = 0x31,
+ BLT_OP_XY_COLOR_BLT = 0x50,
+ BLT_OP_XY_SRC_COPY_BLT = 0x53
};
-enum blt_32bpp_mask {
- BLT_32BPP_MASK_ALPHA = (1 << 0),
- BLT_32BPP_MASK_RGB = (1 << 1)
+enum blt_32bpp_mask
+{
+ BLT_32BPP_MASK_ALPHA = (1 << 0),
+ BLT_32BPP_MASK_RGB = (1 << 1)
};
-enum blt_packing { BLT_PACKING_BIT = 0, BLT_PACKING_BYTE = 1 };
+enum blt_packing
+{
+ BLT_PACKING_BIT = 0,
+ BLT_PACKING_BYTE = 1
+};
-enum blt_color_depth {
- BLT_COLOR_DEPTH_8BIT = 0x0,
- BLT_COLOR_DEPTH_16BIT_565 = 0x1,
- BLT_COLOR_DEPTH_16BIT_1555 = 0x2,
- BLT_COLOR_DEPTH_32BIT = 0x3
+enum blt_color_depth
+{
+ BLT_COLOR_DEPTH_8BIT = 0x0,
+ BLT_COLOR_DEPTH_16BIT_565 = 0x1,
+ BLT_COLOR_DEPTH_16BIT_1555 = 0x2,
+ BLT_COLOR_DEPTH_32BIT = 0x3
};
-enum blt_raster_operation {
- BLT_RASTER_OPERATION_SRC = 0xcc,
- BLT_RASTER_OPERATION_PAT = 0xf0
+enum blt_raster_operation
+{
+ BLT_RASTER_OPERATION_SRC = 0xcc,
+ BLT_RASTER_OPERATION_PAT = 0xf0
};
/* BR00 : BLT Opcode & Control */
-#define BLT_BR00_CLIENT(x) ((x) << 29) /* 31:29 */
-#define BLT_BR00_OP(x) ((x) << 22) /* 28:22 */
-#define BLT_BR00_32BPP_MASK(x) ((x) << 20) /* 21:20 */
- /* 19:17 */
-#define BLT_BR00_PACKING(x) ((x) << 16) /* 16 */
-#define BLT_BR00_SRC_TILING_ENABLE(x) ((x) << 15) /* 15 */
- /* 14:12 */
-#define BLT_BR00_DST_TILING_ENABLE(x) ((x) << 11) /* 11 */
-#define BLT_BR00_DWORD_LENGTH(x) ((x) << 0) /* 7:0 */
+#define BLT_BR00_CLIENT(x) ((x) << 29) /* 31:29 */
+#define BLT_BR00_OP(x) ((x) << 22) /* 28:22 */
+#define BLT_BR00_32BPP_MASK(x) ((x) << 20) /* 21:20 */
+ /* 19:17 */
+#define BLT_BR00_PACKING(x) ((x) << 16) /* 16 */
+#define BLT_BR00_SRC_TILING_ENABLE(x) ((x) << 15) /* 15 */
+ /* 14:12 */
+#define BLT_BR00_DST_TILING_ENABLE(x) ((x) << 11) /* 11 */
+#define BLT_BR00_DWORD_LENGTH(x) ((x) << 0) /* 7:0 */
/* BR01 : Setup BLT Raster OP, Control, and Destination Offset */
-#define BLT_BR01_SOLID_PATTERN(x) ((x) << 31) /* 31 */
-#define BLT_BR01_CLIPPING_ENABLE(x) ((x) << 30) /* 30 */
-#define BLT_BR01_MONO_SRC_TRANSPARENCY(x) ((x) << 29) /* 29 */
-#define BLT_BR01_MONO_PAT_TRANSPARENCY(x) ((x) << 28) /* 28 */
-#define BLT_BR01_COLOR_DEPTH(x) ((x) << 24) /* 25:24 */
-#define BLT_BR01_RASTER_OPERATION(x) ((x) << 16) /* 23:16 */
-#define BLT_BR01_DST_PITCH(x) ((x) << 0) /* 15:0 */
+#define BLT_BR01_SOLID_PATTERN(x) ((x) << 31) /* 31 */
+#define BLT_BR01_CLIPPING_ENABLE(x) ((x) << 30) /* 30 */
+#define BLT_BR01_MONO_SRC_TRANSPARENCY(x) ((x) << 29) /* 29 */
+#define BLT_BR01_MONO_PAT_TRANSPARENCY(x) ((x) << 28) /* 28 */
+#define BLT_BR01_COLOR_DEPTH(x) ((x) << 24) /* 25:24 */
+#define BLT_BR01_RASTER_OPERATION(x) ((x) << 16) /* 23:16 */
+#define BLT_BR01_DST_PITCH(x) ((x) << 0) /* 15:0 */
/* BR05 : Setup Expansion Background Color */
-#define BLT_BR05_BACKGROUND_COLOR(x) ((x) << 0) /* 31:0 */
+#define BLT_BR05_BACKGROUND_COLOR(x) ((x) << 0) /* 31:0 */
/* BR06 : Setup Expansion Foreground Color */
-#define BLT_BR06_FOREGROUND_COLOR(x) ((x) << 0) /* 31:0 */
+#define BLT_BR06_FOREGROUND_COLOR(x) ((x) << 0) /* 31:0 */
-/* BR07 : Setup Blit Color Pattern Address */
-/* 31:29 */
-#define BLT_BR07_PAT_ADDRESS(x) ((x) << 6) /* 28:6 */
- /* 5:0 */
+/* BR07 : Setup Blit Color Pattern Address Low Bits */
+ /* 31:29 */
+#define BLT_BR07_PAT_ADDRESS(x) ((x) << 6) /* 28:6 */
+ /* 5:0 */
-/* BR09 : Destination Address */
-/* 31:29 */
-#define BLT_BR09_DST_ADDRESS(x) ((x) << 0) /* 28:0 */
+/* BR09 : Destination Address Low Bits */
+ /* 31:29 */
+#define BLT_BR09_DST_ADDRESS(x) ((x) << 0) /* 28:0 */
/* BR11 : Source Pitch */
-/* 31:16 */
-#define BLT_BR11_SRC_PITCH(x) ((x) << 0) /* 15:0 */
+ /* 31:16 */
+#define BLT_BR11_SRC_PITCH(x) ((x) << 0) /* 15:0 */
-/* BR12 : Source Address */
-/* 31:29 */
-#define BLT_BR12_SRC_ADDRESS(x) ((x) << 0) /* 28:0 */
+/* BR12 : Source Address Low Bits */
+ /* 31:29 */
+#define BLT_BR12_SRC_ADDRESS(x) ((x) << 0) /* 28:0 */
/* BR13 : BLT Raster OP, Control, and Destination Pitch */
-#define BLT_BR13_SOLID_PATTERN(x) ((x) << 31) /* 31 */
-#define BLT_BR13_CLIPPING_ENABLE(x) ((x) << 30) /* 30 */
-#define BLT_BR13_MONO_SRC_TRANSPARENT(x) ((x) << 29) /* 29 */
-#define BLT_BR13_MONO_PAT_TRANSPARENT(x) ((x) << 28) /* 28 */
-#define BLT_BR13_COLOR_DEPTH(x) ((x) << 24) /* 25:24 */
-#define BLT_BR13_RASTER_OPERATION(x) ((x) << 16) /* 23:16 */
-#define BLT_BR13_DST_PITCH(x) ((x) << 0) /* 15:0 */
+#define BLT_BR13_SOLID_PATTERN(x) ((x) << 31) /* 31 */
+#define BLT_BR13_CLIPPING_ENABLE(x) ((x) << 30) /* 30 */
+#define BLT_BR13_MONO_SRC_TRANSPARENT(x) ((x) << 29) /* 29 */
+#define BLT_BR13_MONO_PAT_TRANSPARENT(x) ((x) << 28) /* 28 */
+#define BLT_BR13_COLOR_DEPTH(x) ((x) << 24) /* 25:24 */
+#define BLT_BR13_RASTER_OPERATION(x) ((x) << 16) /* 23:16 */
+#define BLT_BR13_DST_PITCH(x) ((x) << 0) /* 15:0 */
/* BR16 : Pattern Expansion Background & Solid Pattern Color */
-#define BLT_BR16_COLOR(x) ((x) << 0) /* 31 : 0 */
+#define BLT_BR16_COLOR(x) ((x) << 0) /* 31 : 0 */
/* BR22 : Destination Top Left */
-#define BLT_BR22_DST_Y1(x) ((x) << 16) /* 31:16 */
-#define BLT_BR22_DST_X1(x) ((x) << 0) /* 16:0 */
+#define BLT_BR22_DST_Y1(x) ((x) << 16) /* 31:16 */
+#define BLT_BR22_DST_X1(x) ((x) << 0) /* 16:0 */
/* BR23 : Destination Bottom Right */
-#define BLT_BR23_DST_Y2(x) ((x) << 16) /* 31:16 */
-#define BLT_BR23_DST_X2(x) ((x) << 0) /* 16:0 */
+#define BLT_BR23_DST_Y2(x) ((x) << 16) /* 31:16 */
+#define BLT_BR23_DST_X2(x) ((x) << 0) /* 16:0 */
/* BR24 : Clip Rectangle Top Left */
-/* 31 */
-#define BLT_BR24_CLP_Y1(x) ((x) << 16) /* 30:16 */
- /* 15 */
-#define BLT_BR24_CLP_X1(x) ((x) << 0) /* 14:0 */
+ /* 31 */
+#define BLT_BR24_CLP_Y1(x) ((x) << 16) /* 30:16 */
+ /* 15 */
+#define BLT_BR24_CLP_X1(x) ((x) << 0) /* 14:0 */
/* BR25 : Clip Rectangle Bottom Right */
-/* 31 */
-#define BLT_BR25_CLP_Y2(x) ((x) << 16) /* 30:16 */
- /* 15 */
-#define BLT_BR25_CLP_X2(x) ((x) << 0) /* 14:0 */
+ /* 31 */
+#define BLT_BR25_CLP_Y2(x) ((x) << 16) /* 30:16 */
+ /* 15 */
+#define BLT_BR25_CLP_X2(x) ((x) << 0) /* 14:0 */
/* BR26 : Source Top Left */
-#define BLT_BR26_SRC_Y1(x) ((x) << 16) /* 31:16 */
-#define BLT_BR26_SRC_X1(x) ((x) << 0) /* 15:0 */
-
-static inline void
-xy_setup_blt(struct intel_batch *batch, bool monochrome_source_transparency,
- uint8_t raster_operation, uint32_t background_color,
- uint32_t foreground_color, drm_intel_bo *dst, uint16_t dst_pitch) {
- uint32_t tiling_mode, swizzle_mode;
-
- intel_batch_ensure_space(batch, 8);
-
- drm_intel_bo_get_tiling(dst, &tiling_mode, &swizzle_mode);
- drm_intel_bo_emit_reloc_fence(batch->bo, intel_batch_offset(batch, 4), dst, 0,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
-
- intel_batch_add_dwords(
- batch, 8,
- BLT_BR00_CLIENT(INTEL_CLIENT_BLT) | BLT_BR00_OP(BLT_OP_XY_SETUP_BLT) |
- BLT_BR00_32BPP_MASK(BLT_32BPP_MASK_ALPHA | BLT_32BPP_MASK_RGB) |
- BLT_BR00_DST_TILING_ENABLE(tiling_mode != I915_TILING_NONE) |
- BLT_BR00_DWORD_LENGTH(6),
-
- BLT_BR01_CLIPPING_ENABLE(false) |
- BLT_BR01_MONO_SRC_TRANSPARENCY(monochrome_source_transparency) |
- BLT_BR01_COLOR_DEPTH(BLT_COLOR_DEPTH_32BIT) |
- BLT_BR01_RASTER_OPERATION(raster_operation) |
- BLT_BR01_DST_PITCH(tiling_mode == I915_TILING_NONE ? dst_pitch
- : dst_pitch >> 2),
-
- /* XXX: No clipping yet */
- BLT_BR24_CLP_Y1(0) | BLT_BR24_CLP_X1(0),
-
- BLT_BR25_CLP_Y2(0) | BLT_BR25_CLP_X2(0),
-
- BLT_BR09_DST_ADDRESS(dst->offset),
- BLT_BR05_BACKGROUND_COLOR(background_color),
- BLT_BR06_FOREGROUND_COLOR(foreground_color), BLT_BR07_PAT_ADDRESS(0));
+#define BLT_BR26_SRC_Y1(x) ((x) << 16) /* 31:16 */
+#define BLT_BR26_SRC_X1(x) ((x) << 0) /* 15:0 */
+
+/* BR27 : Destination Address High Bits */
+ /* 31:16 */
+#define BLT_BR27_DST_ADDRESS_HI(x) ((x) << 0) /* 15:0 */
+
+/* BR28 : Source Address High Bits */
+ /* 31:16 */
+#define BLT_BR28_SRC_ADDRESS_HI(x) ((x) << 0) /* 15:0 */
+
+/* BR30 : Setup Blit Color Pattern Address High Bits */
+ /* 31:16 */
+#define BLT_BR30_PAT_ADDRESS_HI(x) ((x) << 0) /* 15:0 */
+
+static inline void xy_setup_blt(struct intel_batch * batch,
+ bool monochrome_source_transparency,
+ uint8_t raster_operation,
+ uint32_t background_color,
+ uint32_t foreground_color,
+ drm_intel_bo * dst, uint16_t dst_pitch)
+{
+ uint32_t tiling_mode, swizzle_mode;
+
+ intel_batch_ensure_space(batch, GEN(batch, 8) ? 10 : 8);
+
+ drm_intel_bo_get_tiling(dst, &tiling_mode, &swizzle_mode);
+ drm_intel_bo_emit_reloc_fence
+ (batch->bo, intel_batch_offset(batch, 4), dst, 0,
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
+
+ intel_batch_add_dwords(batch, 4,
+ BLT_BR00_CLIENT(INTEL_CLIENT_BLT)
+ | BLT_BR00_OP(BLT_OP_XY_SETUP_BLT)
+ | BLT_BR00_32BPP_MASK(BLT_32BPP_MASK_ALPHA | BLT_32BPP_MASK_RGB)
+ | BLT_BR00_DST_TILING_ENABLE(tiling_mode != I915_TILING_NONE)
+ | BLT_BR00_DWORD_LENGTH(GEN(batch, 8) ? 8 : 6),
+
+ BLT_BR01_CLIPPING_ENABLE(false)
+ | BLT_BR01_MONO_SRC_TRANSPARENCY(monochrome_source_transparency)
+ | BLT_BR01_COLOR_DEPTH(BLT_COLOR_DEPTH_32BIT)
+ | BLT_BR01_RASTER_OPERATION(raster_operation)
+ | BLT_BR01_DST_PITCH(tiling_mode == I915_TILING_NONE
+ ? dst_pitch : dst_pitch >> 2),
+
+ /* XXX: No clipping yet */
+ BLT_BR24_CLP_Y1(0)
+ | BLT_BR24_CLP_X1(0),
+
+ BLT_BR25_CLP_Y2(0)
+ | BLT_BR25_CLP_X2(0)
+ );
+
+ intel_batch_add_dwords(batch, GEN(batch, 8) ? 2 : 1,
+ BLT_BR09_DST_ADDRESS(dst->offset64),
+ /* if gen8 */
+ BLT_BR27_DST_ADDRESS_HI(dst->offset64 >> 32)
+ );
+
+ intel_batch_add_dwords(batch, 2,
+ BLT_BR05_BACKGROUND_COLOR(background_color),
+ BLT_BR06_FOREGROUND_COLOR(foreground_color)
+ );
+
+ intel_batch_add_dwords(batch, GEN(batch, 8) ? 2 : 1,
+ BLT_BR07_PAT_ADDRESS(0),
+ /* if gen8 */
+ BLT_BR30_PAT_ADDRESS_HI(0)
+ );
}
-static inline int xy_text_blt(struct intel_batch *batch, drm_intel_bo *src,
- uint32_t src_offset, drm_intel_bo *dst,
- int16_t dst_x1, int16_t dst_y1, int16_t dst_x2,
- int16_t dst_y2) {
- uint32_t tiling_mode, swizzle_mode;
-
- if (!intel_batch_check_space(batch, 4))
- return INTEL_BATCH_NO_SPACE;
-
- drm_intel_bo_get_tiling(dst, &tiling_mode, &swizzle_mode);
-
- drm_intel_bo_emit_reloc_fence(batch->bo, intel_batch_offset(batch, 3), src,
- src_offset, I915_GEM_DOMAIN_RENDER, 0);
-
- intel_batch_add_dwords(
- batch, 4,
- BLT_BR00_CLIENT(INTEL_CLIENT_BLT) | BLT_BR00_OP(BLT_OP_XY_TEXT_BLT) |
- BLT_BR00_PACKING(BLT_PACKING_BYTE) |
- BLT_BR00_DST_TILING_ENABLE(tiling_mode != I915_TILING_NONE) |
- BLT_BR00_DWORD_LENGTH(2),
-
- BLT_BR22_DST_Y1(dst_y1) | BLT_BR22_DST_X1(dst_x1),
- BLT_BR23_DST_Y2(dst_y2) | BLT_BR23_DST_X2(dst_x2),
- BLT_BR12_SRC_ADDRESS(src->offset + src_offset));
-
- return INTEL_BATCH_SUCCESS;
+static inline int xy_text_blt(struct intel_batch * batch,
+ drm_intel_bo * src, uint32_t src_offset,
+ drm_intel_bo * dst,
+ int16_t dst_x1, int16_t dst_y1,
+ int16_t dst_x2, int16_t dst_y2)
+{
+ uint32_t tiling_mode, swizzle_mode;
+
+ if (!intel_batch_check_space(batch, GEN(batch, 8) ? 5 : 4))
+ return INTEL_BATCH_NO_SPACE;
+
+ drm_intel_bo_get_tiling(dst, &tiling_mode, &swizzle_mode);
+
+ drm_intel_bo_emit_reloc_fence
+ (batch->bo, intel_batch_offset(batch, 3), src, src_offset,
+ I915_GEM_DOMAIN_RENDER, 0);
+
+ intel_batch_add_dwords(batch, 3,
+ BLT_BR00_CLIENT(INTEL_CLIENT_BLT)
+ | BLT_BR00_OP(BLT_OP_XY_TEXT_BLT)
+ | BLT_BR00_PACKING(BLT_PACKING_BYTE)
+ | BLT_BR00_DST_TILING_ENABLE(tiling_mode != I915_TILING_NONE)
+ | BLT_BR00_DWORD_LENGTH(GEN(batch, 8) ? 3 : 2),
+
+ BLT_BR22_DST_Y1(dst_y1) | BLT_BR22_DST_X1(dst_x1),
+ BLT_BR23_DST_Y2(dst_y2) | BLT_BR23_DST_X2(dst_x2)
+ );
+
+ intel_batch_add_dwords(batch, GEN(batch, 8) ? 2 : 1,
+ BLT_BR12_SRC_ADDRESS(src->offset64 + src_offset),
+ /* if gen8 */
+ BLT_BR28_SRC_ADDRESS_HI((src->offset64 + src_offset) >> 32)
+ );
+
+ return INTEL_BATCH_SUCCESS;
}
-static inline int xy_text_immediate_blt(struct intel_batch *batch,
- drm_intel_bo *dst, int16_t dst_x1,
- int16_t dst_y1, int16_t dst_x2,
- int16_t dst_y2, uint16_t count,
- uint32_t *immediates) {
- /* Round up to the next even number. */
- uint8_t dwords = (count + 1) & ~1;
- uint32_t index;
- uint32_t tiling_mode, swizzle_mode;
-
- if (!intel_batch_check_space(batch, 3 + dwords))
- return INTEL_BATCH_NO_SPACE;
-
- drm_intel_bo_get_tiling(dst, &tiling_mode, &swizzle_mode);
-
- intel_batch_add_dwords(
- batch, 3,
- BLT_BR00_CLIENT(INTEL_CLIENT_BLT) |
- BLT_BR00_OP(BLT_OP_XY_TEXT_IMMEDIATE_BLT) |
- BLT_BR00_PACKING(BLT_PACKING_BYTE) |
- BLT_BR00_DST_TILING_ENABLE(tiling_mode != I915_TILING_NONE) |
- BLT_BR00_DWORD_LENGTH(1 + dwords),
-
- BLT_BR22_DST_Y1(dst_y1) | BLT_BR22_DST_X1(dst_x1),
- BLT_BR23_DST_Y2(dst_y2) | BLT_BR23_DST_X2(dst_x2));
-
- for (index = 0; index < count; ++index)
- intel_batch_add_dword(batch, *immediates++);
-
- /* From BLT engine documentation:
- *
- * The IMMEDIATE_BLT data MUST transfer an even number of doublewords. The
- * BLT engine will hang if it does not get an even number of doublewords. */
- if (count & 1)
- intel_batch_add_dword(batch, 0);
-
- return INTEL_BATCH_SUCCESS;
+static inline int xy_text_immediate_blt(struct intel_batch * batch,
+ drm_intel_bo * dst,
+ int16_t dst_x1, int16_t dst_y1,
+ int16_t dst_x2, int16_t dst_y2,
+ uint16_t count, uint32_t * immediates)
+{
+ /* Round up to the next even number. */
+ uint8_t dwords = (count + 1) & ~1;
+ uint32_t index;
+ uint32_t tiling_mode, swizzle_mode;
+
+ if (!intel_batch_check_space(batch, 3 + dwords))
+ return INTEL_BATCH_NO_SPACE;
+
+ drm_intel_bo_get_tiling(dst, &tiling_mode, &swizzle_mode);
+
+ intel_batch_add_dwords(batch, 3,
+ BLT_BR00_CLIENT(INTEL_CLIENT_BLT)
+ | BLT_BR00_OP(BLT_OP_XY_TEXT_IMMEDIATE_BLT)
+ | BLT_BR00_PACKING(BLT_PACKING_BYTE)
+ | BLT_BR00_DST_TILING_ENABLE(tiling_mode != I915_TILING_NONE)
+ | BLT_BR00_DWORD_LENGTH(1 + dwords),
+
+ BLT_BR22_DST_Y1(dst_y1) | BLT_BR22_DST_X1(dst_x1),
+ BLT_BR23_DST_Y2(dst_y2) | BLT_BR23_DST_X2(dst_x2)
+ );
+
+ for (index = 0; index < count; ++index)
+ intel_batch_add_dword(batch, *immediates++);
+
+ /* From BLT engine documentation:
+ *
+ * The IMMEDIATE_BLT data MUST transfer an even number of doublewords. The
+ * BLT engine will hang if it does not get an even number of doublewords. */
+ if (count & 1)
+ intel_batch_add_dword(batch, 0);
+
+ return INTEL_BATCH_SUCCESS;
}
-static inline void xy_src_copy_blt(struct intel_batch *batch, drm_intel_bo *src,
- uint16_t src_pitch, uint16_t src_x,
- uint16_t src_y, drm_intel_bo *dst,
- uint16_t dst_pitch, uint16_t dst_x,
- uint16_t dst_y, uint16_t width,
- uint16_t height) {
- uint32_t src_tiling_mode, dst_tiling_mode, swizzle;
-
- intel_batch_ensure_space(batch, 8);
-
- drm_intel_bo_get_tiling(dst, &dst_tiling_mode, &swizzle);
- drm_intel_bo_get_tiling(src, &src_tiling_mode, &swizzle);
-
- drm_intel_bo_emit_reloc_fence(batch->bo, intel_batch_offset(batch, 4), dst, 0,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
- drm_intel_bo_emit_reloc_fence(batch->bo, intel_batch_offset(batch, 7), src, 0,
- I915_GEM_DOMAIN_RENDER, 0);
-
- intel_batch_add_dwords(
- batch, 8,
- BLT_BR00_CLIENT(INTEL_CLIENT_BLT) | BLT_BR00_OP(BLT_OP_XY_SRC_COPY_BLT) |
- BLT_BR00_32BPP_MASK(BLT_32BPP_MASK_ALPHA | BLT_32BPP_MASK_RGB) |
- BLT_BR00_SRC_TILING_ENABLE(src_tiling_mode != I915_TILING_NONE) |
- BLT_BR00_DST_TILING_ENABLE(dst_tiling_mode != I915_TILING_NONE) |
- BLT_BR00_DWORD_LENGTH(6),
-
- BLT_BR13_CLIPPING_ENABLE(false) |
- BLT_BR13_COLOR_DEPTH(BLT_COLOR_DEPTH_32BIT) |
- BLT_BR13_RASTER_OPERATION(BLT_RASTER_OPERATION_SRC) |
- BLT_BR13_DST_PITCH(
- dst_tiling_mode == I915_TILING_NONE ? dst_pitch : dst_pitch >> 2),
-
- BLT_BR22_DST_Y1(dst_y) | BLT_BR22_DST_X1(dst_x),
-
- BLT_BR23_DST_Y2(dst_y + height) | BLT_BR23_DST_X2(dst_x + width),
-
- BLT_BR09_DST_ADDRESS(dst->offset),
- BLT_BR26_SRC_Y1(src_y) | BLT_BR26_SRC_X1(src_x),
- BLT_BR11_SRC_PITCH(src_tiling_mode == I915_TILING_NONE ? src_pitch
- : src_pitch >> 2),
- BLT_BR12_SRC_ADDRESS(src->offset));
+static inline void xy_src_copy_blt(struct intel_batch * batch,
+ drm_intel_bo * src, uint16_t src_pitch,
+ uint16_t src_x, uint16_t src_y,
+ drm_intel_bo * dst, uint16_t dst_pitch,
+ uint16_t dst_x, uint16_t dst_y,
+ uint16_t width, uint16_t height)
+{
+ uint32_t src_tiling_mode, dst_tiling_mode, swizzle;
+
+ intel_batch_ensure_space(batch, GEN(batch, 8) ? 10 : 8);
+
+ drm_intel_bo_get_tiling(dst, &dst_tiling_mode, &swizzle);
+ drm_intel_bo_get_tiling(src, &src_tiling_mode, &swizzle);
+
+ drm_intel_bo_emit_reloc_fence
+ (batch->bo, intel_batch_offset(batch, 4), dst, 0,
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
+ drm_intel_bo_emit_reloc_fence
+ (batch->bo, intel_batch_offset(batch, GEN(batch, 8) ? 8 : 7), src, 0,
+ I915_GEM_DOMAIN_RENDER, 0);
+
+ intel_batch_add_dwords(batch, 4,
+ BLT_BR00_CLIENT(INTEL_CLIENT_BLT)
+ | BLT_BR00_OP(BLT_OP_XY_SRC_COPY_BLT)
+ | BLT_BR00_32BPP_MASK(BLT_32BPP_MASK_ALPHA | BLT_32BPP_MASK_RGB)
+ | BLT_BR00_SRC_TILING_ENABLE(src_tiling_mode != I915_TILING_NONE)
+ | BLT_BR00_DST_TILING_ENABLE(dst_tiling_mode != I915_TILING_NONE)
+ | BLT_BR00_DWORD_LENGTH(GEN(batch, 8) ? 8 : 6),
+
+ BLT_BR13_CLIPPING_ENABLE(false)
+ | BLT_BR13_COLOR_DEPTH(BLT_COLOR_DEPTH_32BIT)
+ | BLT_BR13_RASTER_OPERATION(BLT_RASTER_OPERATION_SRC)
+ | BLT_BR13_DST_PITCH(dst_tiling_mode == I915_TILING_NONE
+ ? dst_pitch : dst_pitch >> 2),
+
+ BLT_BR22_DST_Y1(dst_y) | BLT_BR22_DST_X1(dst_x),
+
+ BLT_BR23_DST_Y2(dst_y + height)
+ | BLT_BR23_DST_X2(dst_x + width)
+ );
+ intel_batch_add_dwords(batch, GEN(batch, 8) ? 2 : 1,
+ BLT_BR09_DST_ADDRESS(dst->offset64),
+ BLT_BR27_DST_ADDRESS_HI(dst->offset64 >> 32)
+ );
+ intel_batch_add_dwords(batch, 2,
+ BLT_BR26_SRC_Y1(src_y) | BLT_BR26_SRC_X1(src_x),
+ BLT_BR11_SRC_PITCH(src_tiling_mode == I915_TILING_NONE
+ ? src_pitch : src_pitch >> 2)
+ );
+ intel_batch_add_dwords(batch, GEN(batch, 8) ? 2 : 1,
+ BLT_BR12_SRC_ADDRESS(src->offset64),
+ BLT_BR28_SRC_ADDRESS_HI(src->offset64 >> 32)
+ );
}
-static inline void xy_color_blt(struct intel_batch *batch, drm_intel_bo *dst,
- uint16_t dst_pitch, uint16_t dst_x1,
- uint16_t dst_y1, uint16_t dst_x2,
- uint16_t dst_y2, uint32_t color) {
- uint32_t tiling_mode, swizzle_mode;
-
- intel_batch_ensure_space(batch, 6);
-
- drm_intel_bo_get_tiling(dst, &tiling_mode, &swizzle_mode);
-
- drm_intel_bo_emit_reloc_fence(batch->bo, intel_batch_offset(batch, 4), dst, 0,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
-
- intel_batch_add_dwords(
- batch, 6,
- BLT_BR00_CLIENT(INTEL_CLIENT_BLT) | BLT_BR00_OP(BLT_OP_XY_COLOR_BLT) |
- BLT_BR00_32BPP_MASK(BLT_32BPP_MASK_ALPHA | BLT_32BPP_MASK_RGB) |
- BLT_BR00_DST_TILING_ENABLE(tiling_mode != I915_TILING_NONE) |
- BLT_BR00_DWORD_LENGTH(4),
-
- BLT_BR13_CLIPPING_ENABLE(false) |
- BLT_BR13_COLOR_DEPTH(BLT_COLOR_DEPTH_32BIT) |
- BLT_BR13_RASTER_OPERATION(BLT_RASTER_OPERATION_PAT) |
- BLT_BR13_DST_PITCH(tiling_mode == I915_TILING_NONE ? dst_pitch
- : dst_pitch >> 2),
-
- BLT_BR22_DST_Y1(dst_y1) | BLT_BR22_DST_X1(dst_x1),
- BLT_BR23_DST_Y2(dst_y2) | BLT_BR23_DST_X2(dst_x2),
- BLT_BR09_DST_ADDRESS(dst->offset), BLT_BR16_COLOR(color));
+static inline void xy_color_blt(struct intel_batch * batch,
+ drm_intel_bo * dst, uint16_t dst_pitch,
+ uint16_t dst_x1, uint16_t dst_y1,
+ uint16_t dst_x2, uint16_t dst_y2,
+ uint32_t color)
+{
+ uint32_t tiling_mode, swizzle_mode;
+
+ intel_batch_ensure_space(batch, GEN(batch, 8) ? 7 : 6);
+
+ drm_intel_bo_get_tiling(dst, &tiling_mode, &swizzle_mode);
+
+ drm_intel_bo_emit_reloc_fence
+ (batch->bo, intel_batch_offset(batch, 4), dst, 0,
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
+
+ intel_batch_add_dwords(batch, 4,
+ BLT_BR00_CLIENT(INTEL_CLIENT_BLT)
+ | BLT_BR00_OP(BLT_OP_XY_COLOR_BLT)
+ | BLT_BR00_32BPP_MASK(BLT_32BPP_MASK_ALPHA | BLT_32BPP_MASK_RGB)
+ | BLT_BR00_DST_TILING_ENABLE(tiling_mode != I915_TILING_NONE)
+ | BLT_BR00_DWORD_LENGTH(GEN(batch, 8) ? 5 : 4),
+
+ BLT_BR13_CLIPPING_ENABLE(false)
+ | BLT_BR13_COLOR_DEPTH(BLT_COLOR_DEPTH_32BIT)
+ | BLT_BR13_RASTER_OPERATION(BLT_RASTER_OPERATION_PAT)
+ | BLT_BR13_DST_PITCH(tiling_mode == I915_TILING_NONE
+ ? dst_pitch : dst_pitch >> 2),
+
+ BLT_BR22_DST_Y1(dst_y1) | BLT_BR22_DST_X1(dst_x1),
+ BLT_BR23_DST_Y2(dst_y2) | BLT_BR23_DST_X2(dst_x2)
+ );
+ intel_batch_add_dwords(batch, GEN(batch, 8) ? 2 : 1,
+ BLT_BR09_DST_ADDRESS(dst->offset64),
+ BLT_BR27_DST_ADDRESS_HI(dst->offset64 >> 32)
+ );
+ intel_batch_add_dword(batch,
+ BLT_BR16_COLOR(color)
+ );
}
#endif
+
diff --git a/src/wld/intel/i965_pci_ids.h b/src/wld/intel/i965_pci_ids.h
index 6126cce..57e70b7 100644
--- a/src/wld/intel/i965_pci_ids.h
+++ b/src/wld/intel/i965_pci_ids.h
@@ -1,18 +1,18 @@
-CHIPSET(0x29A2, i965, "Intel(R) 965G")
-CHIPSET(0x2992, i965, "Intel(R) 965Q")
-CHIPSET(0x2982, i965, "Intel(R) 965G")
-CHIPSET(0x2972, i965, "Intel(R) 946GZ")
-CHIPSET(0x2A02, i965, "Intel(R) 965GM")
-CHIPSET(0x2A12, i965, "Intel(R) 965GME/GLE")
-CHIPSET(0x2A42, g4x, "Mobile IntelĀ® GM45 Express Chipset")
-CHIPSET(0x2E02, g4x, "Intel(R) Integrated Graphics Device")
-CHIPSET(0x2E12, g4x, "Intel(R) Q45/Q43")
-CHIPSET(0x2E22, g4x, "Intel(R) G45/G43")
-CHIPSET(0x2E32, g4x, "Intel(R) G41")
-CHIPSET(0x2E42, g4x, "Intel(R) B43")
-CHIPSET(0x2E92, g4x, "Intel(R) B43")
-CHIPSET(0x0042, ilk, "Intel(R) Ironlake Desktop")
-CHIPSET(0x0046, ilk, "Intel(R) Ironlake Mobile")
+CHIPSET(0x29A2, i965, "Intel(R) 965G")
+CHIPSET(0x2992, i965, "Intel(R) 965Q")
+CHIPSET(0x2982, i965, "Intel(R) 965G")
+CHIPSET(0x2972, i965, "Intel(R) 946GZ")
+CHIPSET(0x2A02, i965, "Intel(R) 965GM")
+CHIPSET(0x2A12, i965, "Intel(R) 965GME/GLE")
+CHIPSET(0x2A42, g4x, "Mobile IntelĀ® GM45 Express Chipset")
+CHIPSET(0x2E02, g4x, "Intel(R) Integrated Graphics Device")
+CHIPSET(0x2E12, g4x, "Intel(R) Q45/Q43")
+CHIPSET(0x2E22, g4x, "Intel(R) G45/G43")
+CHIPSET(0x2E32, g4x, "Intel(R) G41")
+CHIPSET(0x2E42, g4x, "Intel(R) B43")
+CHIPSET(0x2E92, g4x, "Intel(R) B43")
+CHIPSET(0x0042, ilk, "Intel(R) Ironlake Desktop")
+CHIPSET(0x0046, ilk, "Intel(R) Ironlake Mobile")
CHIPSET(0x0102, snb_gt1, "Intel(R) Sandybridge Desktop")
CHIPSET(0x0112, snb_gt2, "Intel(R) Sandybridge Desktop")
CHIPSET(0x0122, snb_gt2, "Intel(R) Sandybridge Desktop")
@@ -86,8 +86,105 @@ CHIPSET(0x0D2B, hsw_gt3, "Intel(R) Haswell")
CHIPSET(0x0D0E, hsw_gt1, "Intel(R) Haswell")
CHIPSET(0x0D1E, hsw_gt2, "Intel(R) Haswell")
CHIPSET(0x0D2E, hsw_gt3, "Intel(R) Haswell")
-CHIPSET(0x0F31, byt, "Intel(R) Bay Trail")
-CHIPSET(0x0F32, byt, "Intel(R) Bay Trail")
-CHIPSET(0x0F33, byt, "Intel(R) Bay Trail")
-CHIPSET(0x0157, byt, "Intel(R) Bay Trail")
-CHIPSET(0x0155, byt, "Intel(R) Bay Trail")
+CHIPSET(0x0F31, byt, "Intel(R) Bay Trail")
+CHIPSET(0x0F32, byt, "Intel(R) Bay Trail")
+CHIPSET(0x0F33, byt, "Intel(R) Bay Trail")
+CHIPSET(0x0157, byt, "Intel(R) Bay Trail")
+CHIPSET(0x0155, byt, "Intel(R) Bay Trail")
+CHIPSET(0x1602, bdw_gt1, "Intel(R) Broadwell GT1")
+CHIPSET(0x1606, bdw_gt1, "Intel(R) Broadwell GT1")
+CHIPSET(0x160A, bdw_gt1, "Intel(R) Broadwell GT1")
+CHIPSET(0x160B, bdw_gt1, "Intel(R) Broadwell GT1")
+CHIPSET(0x160D, bdw_gt1, "Intel(R) Broadwell GT1")
+CHIPSET(0x160E, bdw_gt1, "Intel(R) Broadwell GT1")
+CHIPSET(0x1612, bdw_gt2, "Intel(R) HD Graphics 5600 (Broadwell GT2)")
+CHIPSET(0x1616, bdw_gt2, "Intel(R) HD Graphics 5500 (Broadwell GT2)")
+CHIPSET(0x161A, bdw_gt2, "Intel(R) Broadwell GT2")
+CHIPSET(0x161B, bdw_gt2, "Intel(R) Broadwell GT2")
+CHIPSET(0x161D, bdw_gt2, "Intel(R) Broadwell GT2")
+CHIPSET(0x161E, bdw_gt2, "Intel(R) HD Graphics 5300 (Broadwell GT2)")
+CHIPSET(0x1622, bdw_gt3, "Intel(R) Iris Pro 6200 (Broadwell GT3e)")
+CHIPSET(0x1626, bdw_gt3, "Intel(R) HD Graphics 6000 (Broadwell GT3)")
+CHIPSET(0x162A, bdw_gt3, "Intel(R) Iris Pro P6300 (Broadwell GT3e)")
+CHIPSET(0x162B, bdw_gt3, "Intel(R) Iris 6100 (Broadwell GT3)")
+CHIPSET(0x162D, bdw_gt3, "Intel(R) Broadwell GT3")
+CHIPSET(0x162E, bdw_gt3, "Intel(R) Broadwell GT3")
+CHIPSET(0x22B0, chv, "Intel(R) HD Graphics (Cherrytrail)")
+CHIPSET(0x22B1, chv, "Intel(R) HD Graphics XXX (Braswell)") /* Overridden in brw_get_renderer_string */
+CHIPSET(0x22B2, chv, "Intel(R) HD Graphics (Cherryview)")
+CHIPSET(0x22B3, chv, "Intel(R) HD Graphics (Cherryview)")
+CHIPSET(0x1902, skl_gt1, "Intel(R) HD Graphics 510 (Skylake GT1)")
+CHIPSET(0x1906, skl_gt1, "Intel(R) HD Graphics 510 (Skylake GT1)")
+CHIPSET(0x190A, skl_gt1, "Intel(R) Skylake GT1")
+CHIPSET(0x190B, skl_gt1, "Intel(R) HD Graphics 510 (Skylake GT1)")
+CHIPSET(0x190E, skl_gt1, "Intel(R) Skylake GT1")
+CHIPSET(0x1912, skl_gt2, "Intel(R) HD Graphics 530 (Skylake GT2)")
+CHIPSET(0x1913, skl_gt2, "Intel(R) Skylake GT2f")
+CHIPSET(0x1915, skl_gt2, "Intel(R) Skylake GT2f")
+CHIPSET(0x1916, skl_gt2, "Intel(R) HD Graphics 520 (Skylake GT2)")
+CHIPSET(0x1917, skl_gt2, "Intel(R) Skylake GT2f")
+CHIPSET(0x191A, skl_gt2, "Intel(R) Skylake GT2")
+CHIPSET(0x191B, skl_gt2, "Intel(R) HD Graphics 530 (Skylake GT2)")
+CHIPSET(0x191D, skl_gt2, "Intel(R) HD Graphics P530 (Skylake GT2)")
+CHIPSET(0x191E, skl_gt2, "Intel(R) HD Graphics 515 (Skylake GT2)")
+CHIPSET(0x1921, skl_gt2, "Intel(R) HD Graphics 520 (Skylake GT2)")
+CHIPSET(0x1923, skl_gt3, "Intel(R) Skylake GT3e")
+CHIPSET(0x1926, skl_gt3, "Intel(R) Iris Graphics 540 (Skylake GT3e)")
+CHIPSET(0x1927, skl_gt3, "Intel(R) Iris Graphics 550 (Skylake GT3e)")
+CHIPSET(0x192A, skl_gt4, "Intel(R) Skylake GT4")
+CHIPSET(0x192B, skl_gt3, "Intel(R) Iris Graphics 555 (Skylake GT3e)")
+CHIPSET(0x192D, skl_gt3, "Intel(R) Iris Graphics P555 (Skylake GT3e)")
+CHIPSET(0x1932, skl_gt4, "Intel(R) Iris Pro Graphics 580 (Skylake GT4e)")
+CHIPSET(0x193A, skl_gt4, "Intel(R) Iris Pro Graphics P580 (Skylake GT4e)")
+CHIPSET(0x193B, skl_gt4, "Intel(R) Iris Pro Graphics 580 (Skylake GT4e)")
+CHIPSET(0x193D, skl_gt4, "Intel(R) Iris Pro Graphics P580 (Skylake GT4e)")
+CHIPSET(0x0A84, bxt, "Intel(R) HD Graphics (Broxton)")
+CHIPSET(0x1A84, bxt, "Intel(R) HD Graphics (Broxton)")
+CHIPSET(0x1A85, bxt_2x6, "Intel(R) HD Graphics (Broxton 2x6)")
+CHIPSET(0x5A84, bxt, "Intel(R) HD Graphics 505 (Broxton)")
+CHIPSET(0x5A85, bxt_2x6, "Intel(R) HD Graphics 500 (Broxton 2x6)")
+CHIPSET(0x5902, kbl_gt1, "Intel(R) HD Graphics 610 (Kaby Lake GT1)")
+CHIPSET(0x5906, kbl_gt1, "Intel(R) HD Graphics 610 (Kaby Lake GT1)")
+CHIPSET(0x590A, kbl_gt1, "Intel(R) Kabylake GT1")
+CHIPSET(0x5908, kbl_gt1, "Intel(R) Kabylake GT1")
+CHIPSET(0x590B, kbl_gt1, "Intel(R) Kabylake GT1")
+CHIPSET(0x590E, kbl_gt1, "Intel(R) Kabylake GT1")
+CHIPSET(0x5913, kbl_gt1_5, "Intel(R) Kabylake GT1.5")
+CHIPSET(0x5915, kbl_gt1_5, "Intel(R) Kabylake GT1.5")
+CHIPSET(0x5917, kbl_gt1_5, "Intel(R) Kabylake GT1.5")
+CHIPSET(0x5912, kbl_gt2, "Intel(R) HD Graphics 630 (Kaby Lake GT2)")
+CHIPSET(0x5916, kbl_gt2, "Intel(R) HD Graphics 620 (Kaby Lake GT2)")
+CHIPSET(0x591A, kbl_gt2, "Intel(R) HD Graphics P630 (Kaby Lake GT2)")
+CHIPSET(0x591B, kbl_gt2, "Intel(R) HD Graphics 630 (Kaby Lake GT2)")
+CHIPSET(0x591D, kbl_gt2, "Intel(R) HD Graphics P630 (Kaby Lake GT2)")
+CHIPSET(0x591E, kbl_gt2, "Intel(R) HD Graphics 615 (Kaby Lake GT2)")
+CHIPSET(0x5921, kbl_gt2, "Intel(R) Kabylake GT2F")
+CHIPSET(0x5923, kbl_gt3, "Intel(R) Kabylake GT3")
+CHIPSET(0x5926, kbl_gt3, "Intel(R) Iris Plus Graphics 640 (Kaby Lake GT3)")
+CHIPSET(0x5927, kbl_gt3, "Intel(R) Iris Plus Graphics 650 (Kaby Lake GT3)")
+CHIPSET(0x593B, kbl_gt4, "Intel(R) Kabylake GT4")
+CHIPSET(0x3184, glk, "Intel(R) HD Graphics (Geminilake)")
+CHIPSET(0x3185, glk_2x6, "Intel(R) HD Graphics (Geminilake 2x6)")
+CHIPSET(0x3E90, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
+CHIPSET(0x3E93, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
+CHIPSET(0x3E91, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
+CHIPSET(0x3E92, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
+CHIPSET(0x3E96, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
+CHIPSET(0x3E9B, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
+CHIPSET(0x3E94, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
+CHIPSET(0x3EA6, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)")
+CHIPSET(0x3EA7, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)")
+CHIPSET(0x3EA8, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)")
+CHIPSET(0x3EA5, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)")
+CHIPSET(0x5A49, cnl_2x8, "Intel(R) HD Graphics (Cannonlake 2x8 GT0.5)")
+CHIPSET(0x5A4A, cnl_2x8, "Intel(R) HD Graphics (Cannonlake 2x8 GT0.5)")
+CHIPSET(0x5A41, cnl_3x8, "Intel(R) HD Graphics (Cannonlake 3x8 GT1)")
+CHIPSET(0x5A42, cnl_3x8, "Intel(R) HD Graphics (Cannonlake 3x8 GT1)")
+CHIPSET(0x5A44, cnl_3x8, "Intel(R) HD Graphics (Cannonlake 3x8 GT1)")
+CHIPSET(0x5A59, cnl_4x8, "Intel(R) HD Graphics (Cannonlake 4x8 GT1.5)")
+CHIPSET(0x5A5A, cnl_4x8, "Intel(R) HD Graphics (Cannonlake 4x8 GT1.5)")
+CHIPSET(0x5A5C, cnl_4x8, "Intel(R) HD Graphics (Cannonlake 4x8 GT1.5)")
+CHIPSET(0x5A50, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
+CHIPSET(0x5A51, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
+CHIPSET(0x5A52, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
+CHIPSET(0x5A54, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
diff --git a/src/wld/intel/intel.c b/src/wld/intel/intel.c
deleted file mode 100644
index 9e16183..0000000
--- a/src/wld/intel/intel.c
+++ /dev/null
@@ -1,358 +0,0 @@
-/* wld: intel.c
- *
- * Copyright (c) 2013, 2014 Michael Forney
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- */
-
-#include "batch.h"
-#include "blt.h"
-#include "wld/drm-private.h"
-#include "wld/drm.h"
-#include "wld/wld-private.h"
-
-#include <i915_drm.h>
-#include <intel_bufmgr.h>
-#include <unistd.h>
-
-struct intel_context {
- struct wld_context base;
- drm_intel_bufmgr *bufmgr;
-};
-
-struct intel_renderer {
- struct wld_renderer base;
- struct intel_batch batch;
- struct intel_buffer *target;
-};
-
-struct intel_buffer {
- struct buffer base;
- struct wld_exporter exporter;
- drm_intel_bo *bo;
-};
-
-#include "../interface/buffer.h"
-#include "../interface/context.h"
-#include "../interface/renderer.h"
-#define DRM_DRIVER_NAME intel
-#include "../interface/drm.h"
-IMPL(intel_context, wld_context)
-IMPL(intel_renderer, wld_renderer)
-IMPL(intel_buffer, wld_buffer)
-
-/**** DRM driver ****/
-bool driver_device_supported(uint32_t vendor_id, uint32_t device_id) {
- return vendor_id == 0x8086;
-}
-
-struct wld_context *driver_create_context(int drm_fd) {
- struct intel_context *context;
-
- context = malloc(sizeof *context);
-
- if (!context)
- goto error0;
-
- context_initialize(&context->base, &wld_context_impl);
- context->bufmgr = drm_intel_bufmgr_gem_init(drm_fd, INTEL_BATCH_SIZE);
-
- if (!context->bufmgr)
- goto error1;
-
- return &context->base;
-
-error1:
- free(context);
-error0:
- return NULL;
-}
-
-/**** Context ****/
-struct wld_renderer *context_create_renderer(struct wld_context *base) {
- struct intel_context *context = intel_context(base);
- struct intel_renderer *renderer;
-
- if (!(renderer = malloc(sizeof *renderer)))
- goto error0;
-
- if (!(intel_batch_initialize(&renderer->batch, context->bufmgr)))
- goto error1;
-
- renderer_initialize(&renderer->base, &wld_renderer_impl);
-
- return &renderer->base;
-
-error1:
- free(renderer);
-error0:
- return NULL;
-}
-
-static bool export(struct wld_exporter *exporter, struct wld_buffer *base,
- uint32_t type, union wld_object *object) {
- struct intel_buffer *buffer = intel_buffer(base);
-
- switch (type) {
- case WLD_DRM_OBJECT_HANDLE:
- object->u32 = buffer->bo->handle;
- return true;
- case WLD_DRM_OBJECT_PRIME_FD:
- if (drm_intel_bo_gem_export_to_prime(buffer->bo, &object->i) != 0)
- return false;
- return true;
- default:
- return false;
- }
-}
-
-static struct buffer *new_buffer(uint32_t width, uint32_t height,
- uint32_t format, uint32_t pitch,
- drm_intel_bo *bo) {
- struct intel_buffer *buffer;
-
- if (!(buffer = malloc(sizeof *buffer)))
- return NULL;
-
- buffer_initialize(&buffer->base, &wld_buffer_impl, width, height, format,
- pitch);
- buffer->bo = bo;
- buffer->exporter.export = &export;
- wld_buffer_add_exporter(&buffer->base.base, &buffer->exporter);
-
- return &buffer->base;
-}
-
-struct buffer *context_create_buffer(struct wld_context *base, uint32_t width,
- uint32_t height, uint32_t format,
- uint32_t flags) {
- struct intel_context *context = intel_context(base);
- struct buffer *buffer;
- drm_intel_bo *bo;
- uint32_t tiling_mode = width >= 128 ? I915_TILING_X : I915_TILING_NONE;
- unsigned long pitch;
-
- bo = drm_intel_bo_alloc_tiled(context->bufmgr, "buffer", width, height, 4,
- &tiling_mode, &pitch, 0);
-
- if (!bo)
- goto error0;
-
- if (!(buffer = new_buffer(width, height, format, pitch, bo)))
- goto error1;
-
- return buffer;
-
-error1:
- drm_intel_bo_unreference(bo);
-error0:
- return NULL;
-}
-
-struct buffer *context_import_buffer(struct wld_context *base, uint32_t type,
- union wld_object object, uint32_t width,
- uint32_t height, uint32_t format,
- uint32_t pitch) {
- struct intel_context *context = intel_context(base);
- struct buffer *buffer;
- drm_intel_bo *bo;
-
- switch (type) {
- case WLD_DRM_OBJECT_PRIME_FD: {
- uint32_t size = width * height * format_bytes_per_pixel(format);
- bo = drm_intel_bo_gem_create_from_prime(context->bufmgr, object.i, size);
- break;
- }
- default:
- bo = NULL;
- };
-
- if (!bo)
- goto error0;
-
- if (!(buffer = new_buffer(width, height, format, pitch, bo)))
- goto error1;
-
- return buffer;
-
-error1:
- drm_intel_bo_unreference(bo);
-error0:
- return NULL;
-}
-
-void context_destroy(struct wld_context *base) {
- struct intel_context *context = intel_context(base);
-
- drm_intel_bufmgr_destroy(context->bufmgr);
- free(context);
-}
-
-/**** Renderer ****/
-uint32_t renderer_capabilities(struct wld_renderer *renderer,
- struct buffer *buffer) {
- if (buffer->base.impl == &wld_buffer_impl)
- return WLD_CAPABILITY_READ | WLD_CAPABILITY_WRITE;
-
- return 0;
-}
-
-bool renderer_set_target(struct wld_renderer *base, struct buffer *buffer) {
- struct intel_renderer *renderer = intel_renderer(base);
-
- if (buffer && buffer->base.impl != &wld_buffer_impl)
- return false;
-
- renderer->target = buffer ? intel_buffer(&buffer->base) : NULL;
-
- return true;
-}
-
-void renderer_fill_rectangle(struct wld_renderer *base, uint32_t color,
- int32_t x, int32_t y, uint32_t width,
- uint32_t height) {
- struct intel_renderer *renderer = intel_renderer(base);
- struct intel_buffer *dst = renderer->target;
-
- xy_color_blt(&renderer->batch, dst->bo, dst->base.base.pitch, x, y, x + width,
- y + height, color);
-}
-
-void renderer_copy_rectangle(struct wld_renderer *base,
- struct buffer *buffer_base, int32_t dst_x,
- int32_t dst_y, int32_t src_x, int32_t src_y,
- uint32_t width, uint32_t height) {
- struct intel_renderer *renderer = intel_renderer(base);
-
- if (buffer_base->base.impl != &wld_buffer_impl)
- return;
-
- struct intel_buffer *src = intel_buffer(&buffer_base->base),
- *dst = renderer->target;
-
- xy_src_copy_blt(&renderer->batch, src->bo, src->base.base.pitch, src_x, src_y,
- dst->bo, dst->base.base.pitch, dst_x, dst_y, width, height);
-}
-
-void renderer_draw_text(struct wld_renderer *base, struct font *font,
- uint32_t color, int32_t x, int32_t y, const char *text,
- uint32_t length, struct wld_extents *extents) {
- struct intel_renderer *renderer = intel_renderer(base);
- struct intel_buffer *dst = renderer->target;
- int ret;
- struct glyph *glyph;
- uint32_t row;
- FT_UInt glyph_index;
- uint32_t c;
- uint8_t immediate[512];
- uint8_t *byte;
- int32_t origin_x = x;
-
- xy_setup_blt(&renderer->batch, true, BLT_RASTER_OPERATION_SRC, 0, color,
- dst->bo, dst->base.base.pitch);
-
- if (length == -1)
- length = strlen(text);
-
- while ((ret = FcUtf8ToUcs4((FcChar8 *)text, &c, length)) > 0 && c != '\0') {
- text += ret;
- length -= ret;
- glyph_index = FT_Get_Char_Index(font->face, c);
-
- if (!font_ensure_glyph(font, glyph_index))
- continue;
-
- glyph = font->glyphs[glyph_index];
-
- if (glyph->bitmap.width == 0 || glyph->bitmap.rows == 0)
- goto advance;
-
- byte = immediate;
-
- /* XY_TEXT_IMMEDIATE requires a pitch with no extra bytes */
- for (row = 0; row < glyph->bitmap.rows; ++row) {
- memcpy(byte, glyph->bitmap.buffer + (row * glyph->bitmap.pitch),
- (glyph->bitmap.width + 7) / 8);
- byte += (glyph->bitmap.width + 7) / 8;
- }
-
- retry:
- ret = xy_text_immediate_blt(
- &renderer->batch, dst->bo, origin_x + glyph->x, y + glyph->y,
- origin_x + glyph->x + glyph->bitmap.width,
- y + glyph->y + glyph->bitmap.rows, (byte - immediate + 3) / 4,
- (uint32_t *)immediate);
-
- if (ret == INTEL_BATCH_NO_SPACE) {
- intel_batch_flush(&renderer->batch);
- xy_setup_blt(&renderer->batch, true, BLT_RASTER_OPERATION_SRC, 0, color,
- dst->bo, dst->base.base.pitch);
- goto retry;
- }
-
- advance:
- origin_x += glyph->advance;
- }
-
- if (extents)
- extents->advance = origin_x - x;
-}
-
-void renderer_flush(struct wld_renderer *base) {
- struct intel_renderer *renderer = intel_renderer(base);
-
- intel_batch_flush(&renderer->batch);
-}
-
-void renderer_destroy(struct wld_renderer *base) {
- struct intel_renderer *renderer = intel_renderer(base);
-
- intel_batch_finalize(&renderer->batch);
- free(renderer);
-}
-
-/**** Buffer ****/
-bool buffer_map(struct buffer *base) {
- struct intel_buffer *buffer = intel_buffer(&base->base);
-
- if (drm_intel_gem_bo_map_gtt(buffer->bo) != 0)
- return false;
-
- buffer->base.base.map = buffer->bo->virtual;
-
- return true;
-}
-
-bool buffer_unmap(struct buffer *base) {
- struct intel_buffer *buffer = intel_buffer(&base->base);
-
- if (drm_intel_gem_bo_unmap_gtt(buffer->bo) != 0)
- return false;
-
- buffer->base.base.map = NULL;
-
- return true;
-}
-
-void buffer_destroy(struct buffer *base) {
- struct intel_buffer *buffer = intel_buffer(&base->base);
-
- drm_intel_bo_unreference(buffer->bo);
- free(buffer);
-}
diff --git a/src/wld/intel/mi.h b/src/wld/intel/mi.h
index da0fcd2..5c830c7 100644
--- a/src/wld/intel/mi.h
+++ b/src/wld/intel/mi.h
@@ -26,24 +26,25 @@
#define INTEL_CLIENT_MI 0x0
-#define MI_OP(opcode) \
- (INTEL_CLIENT_MI << 29 /* 31:29 */ \
- | opcode << 23 /* 28:23 */ \
- )
+#define MI_OP(opcode) ( \
+ INTEL_CLIENT_MI << 29 /* 31:29 */ \
+ | opcode << 23 /* 28:23 */ \
+)
-#define MI_NOOP MI_OP(0x00)
-#define MI_FLUSH MI_OP(0x04)
-#define MI_BATCH_BUFFER_END MI_OP(0x0A)
+#define MI_NOOP MI_OP(0x00)
+#define MI_FLUSH MI_OP(0x04)
+#define MI_BATCH_BUFFER_END MI_OP(0x0A)
/* MI_NOOP */
-#define MI_NOOP_IDENTIFICATION_NUMBER(number) (1 << 22 | number)
+#define MI_NOOP_IDENTIFICATION_NUMBER(number) (1 << 22 | number)
/* MI_FLUSH */
-#define MI_FLUSH_ENABLE_PROTECTED_MEMORY (1 << 6)
-#define MI_FLUSH_DISABLE_INDIRECT_STATE_POINTERS (1 << 5)
-#define MI_FLUSH_CLEAR_GENERIC_MEDIA_STATE (1 << 4)
-#define MI_FLUSH_RESET_GLOBAL_SNAPSHOT_COUNT (1 << 3)
-#define MI_FLUSH_INHIBIT_RENDER_CACHE_FLUSH (1 << 2)
+#define MI_FLUSH_ENABLE_PROTECTED_MEMORY (1 << 6)
+#define MI_FLUSH_DISABLE_INDIRECT_STATE_POINTERS (1 << 5)
+#define MI_FLUSH_CLEAR_GENERIC_MEDIA_STATE (1 << 4)
+#define MI_FLUSH_RESET_GLOBAL_SNAPSHOT_COUNT (1 << 3)
+#define MI_FLUSH_INHIBIT_RENDER_CACHE_FLUSH (1 << 2)
#define MI_FLUSH_INVALIDATE_STATE_INSTRUCTION_CACHE (1 << 1)
#endif
+