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`timescale 1ns / 1ps
module romwb_testbench;
reg wb_clk_i;
reg wb_rst_i;
reg [31:0] wb_dat_i;
reg [31:0] wb_adr_i;
reg wb_we_i;
reg [3:0] wb_sel_i;
reg wb_cyc_i;
reg wb_stb_i;
wire [31:0] wb_dat_o;
wire wb_ack_o;
rom_wb uut (
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
.wb_dat_i(wb_dat_i),
.wb_adr_i(wb_adr_i),
.wb_we_i(wb_we_i),
.wb_sel_i(wb_sel_i),
.wb_cyc_i(wb_cyc_i),
.wb_stb_i(wb_stb_i),
.wb_dat_o(wb_dat_o),
.wb_ack_o(wb_ack_o)
);
initial begin
wb_clk_i = 0;
forever begin
wb_clk_i = !wb_clk_i;
#50;
end
end
reg [31:0] read_value;
localparam ADR = 5'hF,
VAL = 32'habbccdd;
initial begin
wb_sel_i = 0;
wb_rst_i = 0;
clear();
$display( "ROM Wishbone Controller Testbench started." );
$display( "Writing to ROM value 0x%h by address 0x%h...", ADR, VAL );
write( ADR, VAL );
$display( "Writing finished.", );
$display( "Reading from ROM from address 0x%h...", ADR );
read( ADR, read_value );
$display( "Read value is 0x%h", read_value );
$display( "ROM Wishbone Controller Testbench finished." );
clear();
$finish();
end
task write( input [4:0] adr, input [31:0] dat );
begin
@( posedge wb_clk_i );
wb_adr_i <= adr; // master set ADR to 4 for WRITING to ADR
wb_we_i <= 1; // master set WE_I to 1 for WRITING
wb_stb_i <= 1; // master set STB_O to 1 for indicate of start phase
wb_cyc_i <= 1; // master set CYC_O to 1 for indicate of start cycle
wb_dat_i <= dat;
@( posedge wb_clk_i );
while( wb_ack_o == 1'b0 )
@( posedge wb_clk_i );
wb_stb_i <= 1'b0;
wb_cyc_i <= 1'b0;
end
endtask
task read( input [4:0] adr, output [31:0] dat );
begin
@( posedge wb_clk_i );
wb_adr_i <= adr; // master set ADR to 4 for READING from ADR
wb_we_i <= 0; // master set WE_I to 0 for READING
wb_stb_i <= 1; // master set STB_O to 1 for indicate of start phase
wb_cyc_i <= 1; // master set CYC_O to 1 for indicate of start cycle
@( posedge wb_clk_i );
while( wb_ack_o == 1'b0 )
@( posedge wb_clk_i );
dat <= wb_dat_o;
wb_stb_i <= 1'b0;
wb_cyc_i <= 1'b0;
end
endtask
task clear();
begin
@( posedge wb_clk_i );
wb_adr_i <= 0;
wb_we_i <= 0;
wb_stb_i <= 0;
wb_cyc_i <= 0;
wb_sel_i = 0;
wb_rst_i = 0;
end
endtask
endmodule
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