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module rom_ctrl(
input clk_i,
input rst_i,
input rd_i,
input wr_i,
input [31:0] dat_i,
input [4:0] adr_i,
output reg[31:0] dat_o,
output ack_o
);
wire read_buf_wr, write_buf_wr, read_buf_rd, write_buf_rd;
wire read_buf_empty, write_buf_empty, read_buf_full, write_buf_full;
wire read_buf_rst, write_buf_rst;
wire[31:0] read_buf_data_i, write_buf_data_i, read_buf_data_o, write_buf_data_o;
//***********************************
// Controller state
//***********************************
// Memory for storing state
reg[4:0] state = IDLE_S;
reg[4:0] next_state;
// List of states
localparam IDLE_S = 0,
WAIT_S = 1,
WRITING_DATA_S = 2,
READING_DATA_S = 3,
WRITING_STATUS_S = 4,
READING_STATUS_S = 5,
BULK_ERASING_S = 6,
ERASING_SECTOR_S = 7,
READING_REG_S = 8,
WRITING_REG_S = 9,
POPPING_READ_BUFFER_S = 10,
PUSHING_WRITE_BUFFER_S = 11,
CLEARING_READ_BUFFER_S = 12,
CLEARING_WRITE_BUFFER_S = 13;
//***********************************
// Virtual registers
//***********************************
// Memory for storing registers
reg[31:0] registers[31:0];
// List of virtual registers
localparam WADDR = 0,
WDATA = 1,
WLEN = 2,
RADDR = 3,
RDATA = 4,
RLEN = 5,
SEC_ADDR_ERASE = 6,
BULK_ERASE = 7,
STATUS = 8;
//***********************************
// WRITE BUFFER
//***********************************
// Empty WRITE BUFFER when write to WADDR
assign write_buf_rst = ( state == CLEARING_WRITE_BUFFER_S );
// Get data for writing from dat_i
assign write_buf_data_i = dat_i;
// Write to the WRITE BUFFER when write data to WDATA
assign write_buf_wr = ( state == PUSHING_WRITE_BUFFER_S );
fifo write_buf(
.clk_i(clk_i),
.rst_i(write_buf_rst),
.wr_i(write_buf_wr),
.data_i(write_buf_data_i),
.rd_i(write_buf_rd),
.data_o(write_buf_data_o),
.empty_o(write_buf_empty),
.full_o(write_buf_full)
);
//***********************************
// READ BUFFER
//***********************************
// Empty READ BUFFER when write to RADDR
assign read_buf_rst = ( state == CLEARING_READ_BUFFER_S );
// Mark as read top of READ BUFFER when read data from RDATA
assign read_buf_rd = ( state == POPPING_READ_BUFFER_S );
fifo read_buf(
.clk_i(clk_i),
.rst_i(read_buf_rst),
.rd_i(read_buf_rd),
.wr_i(read_buf_wr),
.empty_o(read_buf_empty),
.full_o(read_buf_full),
.data_i(read_buf_data_i),
.data_o(read_buf_data_o)
);
//***********************************
// M25P16 SPI Core
//***********************************
wire spi_finish;
wire[23:0] spi_addr;
assign spi_addr = dat_i[23:0];
reg[4:0] spi_opcode = 0;
m25p16_spi_core spi(
.clk_i( clk_i ),
.opcode_i( spi_opcode ),
.dat_i( write_buf_data_o ),
.dat_o( read_buf_data_i ),
.dat_o_read( write_buf_rd ),
.dat_o_valid( read_buf_wr ),
.adr_i( spi_addr ),
.finish_o(spi_finish),
);
//***********************************
// Virtual Registers I/O
//***********************************
always @( posedge clk_i )
if( state == READING_REG_S )
dat_o <= registers[adr_i];
always @( posedge clk_i )
if( state == WRITING_REG_S ||
adr_i == RADDR ||
adr_i == WADDR ||
adr_i == SEC_ADDR_ERASE )
registers[adr_i] <= dat_i;
//***********************************
// Rom Controller FSM
//***********************************
always @( posedge clk_i, posedge rst_i )
if( rst_i )
state <= IDLE_S;
else
state <= next_state;
always @*
case( next_state )
READING_DATA_S:
spi_opcode = 1;
WRITING_DATA_S:
spi_opcode = 2;
ERASING_SECTOR_S:
spi_opcode = 3;
BULK_ERASING_S:
spi_opcode = 4;
READING_STATUS_S:
spi_opcode = 5;
WRITING_STATUS_S:
spi_opcode = 6;
default:
spi_opcode = 0;
endcase
always @*
begin
next_state = state;
case( state )
IDLE_S:
begin
if( adr_i == RLEN && wr_i )
next_state = READING_DATA_S;
else if( adr_i == RADDR && wr_i )
next_state = CLEARING_READ_BUFFER_S;
else if( adr_i == RDATA && wr_i )
next_state = POPPING_READ_BUFFER_S;
else if( adr_i == WDATA && wr_i )
next_state = PUSHING_WRITE_BUFFER_S;
else if( adr_i == WADDR && wr_i )
next_state = CLEARING_WRITE_BUFFER_S;
else if( adr_i == WLEN && wr_i)
next_state = WRITING_DATA_S;
else if( wr_i && adr_i == SEC_ADDR_ERASE )
next_state = ERASING_SECTOR_S;
else if( wr_i && adr_i == BULK_ERASE )
next_state = BULK_ERASING_S;
else if( rd_i && adr_i == STATUS )
next_state = READING_STATUS_S;
else if( wr_i && adr_i == STATUS )
next_state = WRITING_STATUS_S;
else if( wr_i )
next_state = WRITING_REG_S;
else if( rd_i )
next_state = READING_REG_S;
end
ERASING_SECTOR_S, BULK_ERASING_S, READING_STATUS_S, WRITING_STATUS_S, READING_DATA_S, WRITING_DATA_S:
if( spi_finish )
next_state = WAIT_S;
POPPING_READ_BUFFER_S, CLEARING_READ_BUFFER_S, CLEARING_WRITE_BUFFER_S, PUSHING_WRITE_BUFFER_S, READING_REG_S, WRITING_REG_S:
next_state = WAIT_S;
WAIT_S:
next_state = IDLE_S;
endcase
end
// ACK
assign ack_o = ( state == WAIT_S ? 0 : 1 );
endmodule
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