`timescale 1ns / 1ps

module spicore_testbench;

reg clk_i;
reg rst_i;

reg [4:0]  opcode_i;
reg [31:0] info_i;
reg [31:0] dat_i;
reg [31:0] adr_i;

wire [31:0] dat_o;
wire dat_o_read;
wire dat_o_valid;
wire finish_o;

m25p16_spi_core uut (
  .clk_i(clk_i), 
  .rst_i(rst_i), 
  .opcode_i(opcode_i), 
  .info_i(info_i), 
  .dat_i(dat_i), 
  .dat_o(dat_o), 
  .dat_o_read(dat_o_read), 
  .dat_o_valid(dat_o_valid), 
  .adr_i(adr_i), 
  .finish_o(finish_o)
);

initial begin
  clk_i = 0;
  forever begin
    clk_i = !clk_i;
    #50;
  end
end

initial begin
  clk_i = 0;
  rst_i = 0;
  opcode_i = 0;
  info_i = 0;
  dat_i = 0;
  adr_i = 0;

  #100;
      
  opcode_i = 2;
  info_i   = 32'h00000001;
  dat_i    = 32'hAABBCCDD;
  adr_i    = 32'h00AABBCC;
  
  while( finish_o == 1'b0 )
    @( posedge clk_i );
end

endmodule