hdl/wb_stage.v


1
2
3
4
5
6
7
8
9
10
11

`timescale 1ns / 1ps

module wb_stage(
                input         mem_to_reg,
                input [31:0]  mem_out, alu_out,
                output [31:0] write_data                                
                );

   assign write_data = mem_to_reg ? mem_out : alu_out;
      
endmodule