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`timescale 1ns / 1ps

module wb_rot_ctrl_testbench;

	// Inputs
	reg clk_i;
	reg rst_i;
	reg [31:0] dat_i;
	reg [31:0] adr_i;
	reg we_i;
	reg [3:0] sel_i;
	reg cyc_i;
	reg stb_i;
	reg rot_a_i;
	reg rot_b_i;

	// Outputs
	wire [31:0] dat_o;
	wire ack_o;
	wire [7:0] led;

	// Instantiate the Unit Under Test (UUT)
	wb_rot_ctrl uut (
		.clk_i(clk_i),
		.rst_i(rst_i),
		.dat_i(dat_i),
		.dat_o(dat_o),
		.adr_i(adr_i),
		.we_i(we_i),
		.sel_i(sel_i),
		.cyc_i(cyc_i),
		.stb_i(stb_i),
		.ack_o(ack_o),
		.rot_a_i(rot_a_i),
		.rot_b_i(rot_b_i),
		.led(led)
	);

	initial begin
	  forever begin
	    clk_i = ~clk_i;
		 #100;
	  end
	end

	initial begin
		// Initialize Inputs
		clk_i = 0;
		rst_i = 0;
		dat_i = 0;
		adr_i = 0;
		we_i = 0;
		sel_i = 0;
		cyc_i = 0;
		stb_i = 0;
		rot_a_i = 0;
		rot_b_i = 0;

		// Wait 100 ns for global reset to finish
		#100;

		rst_i = 1;
		#100;
		rst_i = 0;

		#100;
		cyc_i = 1;
		stb_i = 1;
		we_i  = 1;
		adr_i = 1;
		dat_i = 8'b00001111;

		#100;
		#100;
		#100;

		cyc_i = 0;
		stb_i = 0;
	end

endmodule