From 65dfded3a27aa84aa4ec21e755c17e48b3e56033 Mon Sep 17 00:00:00 2001 From: Snuffick Date: Wed, 21 Oct 2015 15:30:14 +0300 Subject: =?UTF-8?q?=D0=98=D0=B7=D0=BC=D0=B5=D0=BD=D0=B5=D0=BD=D0=B8=D1=8F?= =?UTF-8?q?=20=D0=B2=20Makefile.=20=09=D0=A2=D0=B5=D0=BF=D0=B5=D1=80=D1=8C?= =?UTF-8?q?=20=D0=B3=D0=B5=D0=BD=D0=B5=D1=80=D0=B8=D1=80=D1=83=D1=8E=D1=82?= =?UTF-8?q?=D1=81=D1=8F=20=D0=B4=D0=B2=D0=B0=20=D1=84=D0=B0=D0=B9=D0=BB?= =?UTF-8?q?=D0=B0=20=D0=B8=D0=BD=D0=B8=D1=86=D0=B8=D0=B0=D0=BB=D0=B8=D0=B7?= =?UTF-8?q?=D0=B0=D1=86=D0=B8=D0=B8=20(=D0=BE=D0=B4=D0=B8=D0=BD=20=D0=B4?= =?UTF-8?q?=D0=BB=D1=8F=20=D0=B8=D0=BD=D0=B8=D1=86=D0=B8=D0=B0=D0=BB=D0=B8?= =?UTF-8?q?=D0=B7=D0=B0=D1=86=D0=B8=D0=B8=20=D1=81=D0=B5=D0=BA=D1=86=D0=B8?= =?UTF-8?q?=D0=B8=20text,=20=D0=B4=D1=80=D1=83=D0=B3=D0=BE=D0=B9=20-=20?= =?UTF-8?q?=D0=B4=D0=BB=D1=8F=20data).?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Секция text начинается с 0x00000000 как и раньше, секция data - с 0x00001000. Изменения в исходниках mips32. В топ-модуль добавлены локальные параметры границ адресов для секций кода и данных, а также параметризация данных адресов в соответствующих блоках. Секция кода доступна только для чтения. Адреса секции кода (text) по умолчанию - 0x00000000 - 0x00000fff Адреса секции данных (data) по умолчанию - 0x00001000 - 0x0000ffff --- hdl/dp_memory.v | 66 +++++------ hdl/gpio_wb.v | 4 +- hdl/mips_system.v | 85 +++++++------- hdl/ram_wb/ram_wb.v | 100 ++++++++-------- hdl/ram_wb/wb_ram_sc_sw.v | 41 ++++--- hdl/wb/wb.vhd | 286 ++++++++++++++++++++++++---------------------- sw/Makefile | 23 ++-- sw/test.asm | 10 +- 8 files changed, 306 insertions(+), 309 deletions(-) diff --git a/hdl/dp_memory.v b/hdl/dp_memory.v index d4ca2b8..dd5dff9 100644 --- a/hdl/dp_memory.v +++ b/hdl/dp_memory.v @@ -4,52 +4,46 @@ Dual-port Instrcution/Data memory */ -module dp_memory( - input wire clk, - input wire rst, - input wire i_read_en, - input wire [31:0] i_addr, - output wire [31:0] i_instr_out, +module bus_control #( + parameter addr_high = 32'h00000fff, + parameter addr_low = 32'h00000000)( + + input wire clk, + input wire rst, + input wire i_read_en, + input wire [31:0] i_addr, + output wire [31:0] i_instr_out, - output wb_done_o, + output wb_done_o, - input wire d_read_en, - input wire d_write_en, - input wire [31:0] d_addr, - input wire [31:0] d_write_data, - output wire [31:0] d_data_out, + input wire d_read_en, + input wire d_write_en, + input wire [31:0] d_addr, + input wire [31:0] d_write_data, + output wire [31:0] d_data_out, - // wb signals - input [31:0] wbm_dat_i, - input wbm_ack_i, - output [31:0] wbm_dat_o, - output wbm_we_o, - output [3:0] wbm_sel_o, - output [31:0] wbm_adr_o, - output wbm_cyc_o, - output wbm_stb_o +// wb signals + input [31:0] wbm_dat_i, + input wbm_ack_i, + output [31:0] wbm_dat_o, + output wbm_we_o, + output [3:0] wbm_sel_o, + output [31:0] wbm_adr_o, + output wbm_cyc_o, + output wbm_stb_o ); - - localparam mem_high_addr = 32'h00000400; - wire i_bram_select, d_bram_select; + wire i_bram_select; - reg [31:0] mem[0:mem_high_addr - 1]; + reg [31:0] memory[addr_low:addr_high]; initial begin - $readmemh("../../sw/test.rom", mem); + $readmemh("text.rom", memory, addr_low, addr_high); end - assign i_bram_select = (i_addr < mem_high_addr) ? 1'b1 : 1'b0; - assign d_bram_select = (d_addr < mem_high_addr) ? 1'b1 : 1'b0; - - always @(posedge clk) begin - if (d_write_en && d_bram_select) - mem [d_addr] <= d_write_data; - end - - assign i_instr_out = (i_read_en && i_bram_select) ? mem[i_addr] : 0; - //assign d_data_out = (d_read_en && d_bram_select) ? mem[d_addr] : 0; + assign i_bram_select = (i_addr <= addr_high && i_addr >= addr_low) ? 1'b1 : 1'b0; + + assign i_instr_out = (i_read_en && i_bram_select) ? memory[i_addr] : 0; master_wb mwb_inst( diff --git a/hdl/gpio_wb.v b/hdl/gpio_wb.v index 773c1a6..74cafde 100644 --- a/hdl/gpio_wb.v +++ b/hdl/gpio_wb.v @@ -1,4 +1,4 @@ -module gpio_wb( +module gpio_wb #(parameter BASE_ADDR = 32'h00000400) ( // system signals input clk_i, @@ -18,8 +18,6 @@ module gpio_wb( output reg [7:0] gpio_o ); -localparam BASE_ADDR = 32'h00000400; - localparam IDLE = 0; localparam ACK = 1; diff --git a/hdl/mips_system.v b/hdl/mips_system.v index 759500b..ffc61ff 100644 --- a/hdl/mips_system.v +++ b/hdl/mips_system.v @@ -8,6 +8,12 @@ module mips_system ( output [7:0] led ); + localparam [31:0] instr_addr_high = 32'h00000fff, + instr_addr_low = 32'h00000000, + data_addr_high = 32'h0000ffff, + data_addr_low = 32'h00001000, + + gpio_base_addr = 32'h00010000; wire i_read_en; wire [31:0] i_addr; @@ -49,7 +55,7 @@ module mips_system ( wire ram_ack_o; wire [2:0] ram_cti_i = 0; // classic cycle - gpio_wb gpio_inst( + gpio_wb #(gpio_base_addr) gpio_inst( // system signals .clk_i(clk), @@ -67,22 +73,23 @@ module mips_system ( // func signals .gpio_o(led) - ); - - ram_wb ram_inst( - .dat_i(ram_dat_i), - .dat_o(ram_dat_o), - .adr_i(ram_addr_i), - .we_i(ram_we_i), - .sel_i(ram_sel_i), - .cyc_i(ram_cyc_i), - .stb_i(ram_stb_i), - .ack_o(ram_ack_o), - .cti_i(ram_cti_i), - .clk_i(clk), - .rst_i(rst) ); + data_ram_wb #( + .addr_high(data_addr_high), + .addr_low(data_addr_low)) ram_inst( + .dat_i(ram_dat_i), + .dat_o(ram_dat_o), + .adr_i(ram_addr_i), + .we_i(ram_we_i), + .sel_i(ram_sel_i), + .cyc_i(ram_cyc_i), + .stb_i(ram_stb_i), + .ack_o(ram_ack_o), + .cti_i(ram_cti_i), + .clk_i(clk), + .rst_i(rst)); + intercon wb_inst ( // wishbone master port(s) // mips_wbm @@ -118,7 +125,6 @@ module mips_system ( .reset(rst) ); - pipeline pipeline_inst ( .clk(clk), .rst(rst), @@ -132,28 +138,29 @@ module mips_system ( .d_write_data(d_write_data), .d_data_in(d_read_data)); - dp_memory memory_inst ( - .clk(clk), - .rst(rst), - .i_read_en(i_read_en), - .i_addr(i_addr), - .i_instr_out(i_instr), - .d_read_en(d_read_en), - .d_write_en(d_write_en), - .d_addr(d_addr), - .d_write_data(d_write_data), - .d_data_out(d_read_data), - - .wb_done_o(wb_done), - - .wbm_dat_i(mips_wbm_dat_i), - .wbm_ack_i(mips_wbm_ack_i), - .wbm_dat_o(mips_wbm_dat_o), - .wbm_we_o(mips_wbm_we_o), - .wbm_sel_o(mips_wbm_sel_o), - .wbm_adr_o(mips_wbm_adr_o), - .wbm_cyc_o(mips_wbm_cyc_o), - .wbm_stb_o(mips_wbm_stb_o) - ); + bus_control #( + .addr_high(instr_addr_high), + .addr_low(instr_addr_low)) memory_inst ( + .clk(clk), + .rst(rst), + .i_read_en(i_read_en), + .i_addr(i_addr), + .i_instr_out(i_instr), + .d_read_en(d_read_en), + .d_write_en(d_write_en), + .d_addr(d_addr), + .d_write_data(d_write_data), + .d_data_out(d_read_data), + + .wb_done_o(wb_done), + + .wbm_dat_i(mips_wbm_dat_i), + .wbm_ack_i(mips_wbm_ack_i), + .wbm_dat_o(mips_wbm_dat_o), + .wbm_we_o(mips_wbm_we_o), + .wbm_sel_o(mips_wbm_sel_o), + .wbm_adr_o(mips_wbm_adr_o), + .wbm_cyc_o(mips_wbm_cyc_o), + .wbm_stb_o(mips_wbm_stb_o)); endmodule // mips_system diff --git a/hdl/ram_wb/ram_wb.v b/hdl/ram_wb/ram_wb.v index 0f02c08..f581d32 100755 --- a/hdl/ram_wb/ram_wb.v +++ b/hdl/ram_wb/ram_wb.v @@ -1,60 +1,50 @@ -module ram_wb ( dat_i, dat_o, adr_i, we_i, sel_i, cyc_i, stb_i, ack_o, cti_i, clk_i, rst_i); - - parameter dat_width = 32; - parameter adr_width = 10; - parameter mem_size = 1024; +module data_ram_wb #( + parameter addr_high = 32'h0000ffff, + parameter addr_low = 32'h00001000) ( +// wishbone signals + input [31:0] dat_i, + output [31:0] dat_o, + input [31:0] adr_i, + input we_i, + input [3:0] sel_i, + input cyc_i, + input stb_i, + output reg ack_o, + input [2:0] cti_i, +// clock + input clk_i, +// async reset + input rst_i); + + wire [31:0] wr_data; - // wishbone signals - input [31:0] dat_i; - output [31:0] dat_o; - input [adr_width-1:0] adr_i; - input we_i; - input [3:0] sel_i; - input cyc_i; - input stb_i; - output reg ack_o; - input [2:0] cti_i; +// mux for data to ram + assign wr_data[31:24] = sel_i[3] ? dat_i[31:24] : dat_o[31:24]; + assign wr_data[23:16] = sel_i[2] ? dat_i[23:16] : dat_o[23:16]; + assign wr_data[15: 8] = sel_i[1] ? dat_i[15: 8] : dat_o[15: 8]; + assign wr_data[ 7: 0] = sel_i[0] ? dat_i[ 7: 0] : dat_o[ 7: 0]; - // clock - input clk_i; - // async reset - input rst_i; - - wire [31:0] wr_data; - - // mux for data to ram - assign wr_data[31:24] = sel_i[3] ? dat_i[31:24] : dat_o[31:24]; - assign wr_data[23:16] = sel_i[2] ? dat_i[23:16] : dat_o[23:16]; - assign wr_data[15: 8] = sel_i[1] ? dat_i[15: 8] : dat_o[15: 8]; - assign wr_data[ 7: 0] = sel_i[0] ? dat_i[ 7: 0] : dat_o[ 7: 0]; - - ram - # - ( - .dat_width(dat_width), - .adr_width(adr_width), - .mem_size(mem_size) - ) - ram0 - ( - .dat_i(wr_data), - .dat_o(dat_o), - .adr_i(adr_i), - .we_i(we_i & ack_o), - .clk(clk_i) - ); - - // ack_o - always @ (posedge clk_i or posedge rst_i) - if (rst_i) - ack_o <= 1'b0; - else - if (!ack_o) begin - if (cyc_i & stb_i) - ack_o <= 1'b1; end - else - if ((sel_i != 4'b1111) | (cti_i == 3'b000) | (cti_i == 3'b111)) - ack_o <= 1'b0; + ram #(.addr_high(addr_high), + .addr_low(addr_low), + .read_only(1'b0)) data_memory( + + .data_i(wr_data), + .data_o(dat_o), + .addr_i(adr_i), + .wren_i(we_i & ack_o), + .clk_i(clk_i)); + +// ack_o + always @ (posedge clk_i or posedge rst_i) begin + if (rst_i) + ack_o <= 1'b0; + else if (!ack_o) begin + if (cyc_i & stb_i) + ack_o <= 1'b1; + end + else if ((sel_i != 4'b1111) | (cti_i == 3'b000) | (cti_i == 3'b111)) + ack_o <= 1'b0; + end endmodule diff --git a/hdl/ram_wb/wb_ram_sc_sw.v b/hdl/ram_wb/wb_ram_sc_sw.v index c6a9019..cfc807a 100755 --- a/hdl/ram_wb/wb_ram_sc_sw.v +++ b/hdl/ram_wb/wb_ram_sc_sw.v @@ -1,26 +1,25 @@ -module ram (dat_i, dat_o, adr_i, we_i, clk ); - - parameter dat_width = 32; - parameter adr_width = 10; - parameter mem_size = 1024; - - input [dat_width-1:0] dat_i; - input [adr_width-1:0] adr_i; - input we_i; - output reg [dat_width-1:0] dat_o; - input clk; - - reg [dat_width-1:0] ram [0:mem_size - 1] /* synthesis ram_style = no_rw_check */; +module ram #( + parameter addr_high = 32'h00000fff, + parameter addr_low = 32'h00000000, + parameter [0:0] read_only = 1'b0) ( +//Default data_ram has a 1024 words depth. + input [31:0] data_i, + input [31:0] addr_i, + input wren_i, + output reg [31:0] data_o, + input clk_i); - initial begin - $readmemh("../../sw/test.rom", ram); + reg [31:0] memory [addr_low:addr_high] /* synthesis ram_style = no_rw_check */; + + initial begin + $readmemh("data.rom", memory, addr_low, addr_high); end - - always @ (posedge clk) - begin - dat_o <= ram[adr_i]; - if (we_i) - ram[adr_i] <= dat_i; + + always @ (posedge clk_i) begin + data_o <= memory[addr_i]; + + if (wren_i && !read_only) + memory[addr_i] <= data_i; end endmodule // ram diff --git a/hdl/wb/wb.vhd b/hdl/wb/wb.vhd index c54b56e..5f61a90 100644 --- a/hdl/wb/wb.vhd +++ b/hdl/wb/wb.vhd @@ -18,92 +18,100 @@ use IEEE.std_logic_1164.all; package intercon_package is - function "and" ( - l : std_logic_vector; - r : std_logic) -return std_logic_vector; + l : std_logic_vector; + r : std_logic) + + return std_logic_vector; + end intercon_package; + package body intercon_package is function "and" ( - l : std_logic_vector; - r : std_logic) -return std_logic_vector is - variable result : std_logic_vector(l'range); -begin -- "and" - for i in l'range loop - result(i) := l(i) and r; -end loop; -- i -return result; -end "and"; + l : std_logic_vector; + r : std_logic) + + return std_logic_vector is + + variable result : std_logic_vector(l'range); + + begin -- "and" + for i in l'range loop + result(i) := l(i) and r; + end loop; -- i + return result; + end "and"; + end intercon_package; + library IEEE; use IEEE.std_logic_1164.all; entity trafic_supervision is - generic ( - priority : integer := 1; - tot_priority : integer := 2); + generic ( + priority : integer := 1; + tot_priority : integer := 2); - port ( - bg : in std_logic; -- bus grant - ce : in std_logic; -- clock enable - trafic_limit : out std_logic; - clk : in std_logic; - reset : in std_logic); + port ( + bg : in std_logic; -- bus grant + ce : in std_logic; -- clock enable + trafic_limit : out std_logic; + clk : in std_logic; + reset : in std_logic); end trafic_supervision; architecture rtl of trafic_supervision is - signal shreg : std_logic_vector(tot_priority-1 downto 0); - signal cntr : integer range 0 to tot_priority; + signal shreg : std_logic_vector(tot_priority-1 downto 0); + signal cntr : integer range 0 to tot_priority; begin -- rtl - -- purpose: holds information of usage of latest cycles - -- type : sequential - -- inputs : clk, reset, ce, bg - -- outputs: shreg('left) - sh_reg: process (clk,reset) - begin -- process shreg - if reset = '1' then -- asynchronous reset (active hi) - shreg <= (others=>'0'); - elsif clk'event and clk = '1' then -- rising clock edge - if ce='1' then - shreg <= shreg(tot_priority-2 downto 0) & bg; - end if; - end if; - end process sh_reg; - - -- purpose: keeps track of used cycles - -- type : sequential - -- inputs : clk, reset, shreg('left), bg, ce - -- outputs: trafic_limit - counter: process (clk, reset) - begin -- process counter - if reset = '1' then -- asynchronous reset (active hi) - cntr <= 0; - trafic_limit <= '0'; - elsif clk'event and clk = '1' then -- rising clock edge - if ce='1' then - if bg='1' and shreg(tot_priority-1)='0' then - cntr <= cntr + 1; - if cntr=priority-1 then - trafic_limit <= '1'; + -- purpose: holds information of usage of latest cycles + -- type : sequential + -- inputs : clk, reset, ce, bg + -- outputs: shreg('left) + + sh_reg: process (clk,reset) + begin -- process shreg + if reset = '1' then -- asynchronous reset (active hi) + shreg <= (others=>'0'); + elsif clk'event and clk = '1' then -- rising clock edge + if ce='1' then + shreg <= shreg(tot_priority-2 downto 0) & bg; + end if; end if; - elsif bg='0' and shreg(tot_priority-1)='1' then - cntr <= cntr - 1; - if cntr=priority then - trafic_limit <= '0'; + end process sh_reg; + + -- purpose: keeps track of used cycles + -- type : sequential + -- inputs : clk, reset, shreg('left), bg, ce + -- outputs: trafic_limit + + counter: process (clk, reset) + begin -- process counter + if reset = '1' then -- asynchronous reset (active hi) + cntr <= 0; + trafic_limit <= '0'; + elsif clk'event and clk = '1' then -- rising clock edge + if ce='1' then + if bg='1' and shreg(tot_priority-1)='0' then + cntr <= cntr + 1; + if cntr=priority-1 then + trafic_limit <= '1'; + end if; + elsif bg='0' and shreg(tot_priority-1)='1' then + cntr <= cntr - 1; + if cntr=priority then + trafic_limit <= '0'; + end if; + end if; + end if; end if; - end if; - end if; - end if; - end process counter; - + end process counter; end rtl; library IEEE; @@ -111,80 +119,80 @@ use IEEE.std_logic_1164.all; use work.intercon_package.all; entity intercon is - port ( - -- wishbone master port(s) - -- mips_wbm - mips_wbm_dat_i : out std_logic_vector(31 downto 0); - mips_wbm_ack_i : out std_logic; - mips_wbm_dat_o : in std_logic_vector(31 downto 0); - mips_wbm_we_o : in std_logic; - mips_wbm_sel_o : in std_logic_vector(3 downto 0); - mips_wbm_adr_o : in std_logic_vector(31 downto 0); - mips_wbm_cyc_o : in std_logic; - mips_wbm_stb_o : in std_logic; - -- wishbone slave port(s) - -- ram_wbs - ram_wbs_dat_o : in std_logic_vector(31 downto 0); - ram_wbs_ack_o : in std_logic; - ram_wbs_dat_i : out std_logic_vector(31 downto 0); - ram_wbs_we_i : out std_logic; - ram_wbs_sel_i : out std_logic_vector(3 downto 0); - ram_wbs_adr_i : out std_logic_vector(31 downto 0); - ram_wbs_cyc_i : out std_logic; - ram_wbs_stb_i : out std_logic; - -- wbs - wbs_dat_o : in std_logic_vector(31 downto 0); - wbs_ack_o : in std_logic; - wbs_dat_i : out std_logic_vector(31 downto 0); - wbs_we_i : out std_logic; - wbs_sel_i : out std_logic_vector(3 downto 0); - wbs_adr_i : out std_logic_vector(31 downto 0); - wbs_cyc_i : out std_logic; - wbs_stb_i : out std_logic; - -- clock and reset - clk : in std_logic; - reset : in std_logic); + port ( + -- wishbone master port(s) + -- mips_wbm + mips_wbm_dat_i : out std_logic_vector(31 downto 0); + mips_wbm_ack_i : out std_logic; + mips_wbm_dat_o : in std_logic_vector(31 downto 0); + mips_wbm_we_o : in std_logic; + mips_wbm_sel_o : in std_logic_vector(3 downto 0); + mips_wbm_adr_o : in std_logic_vector(31 downto 0); + mips_wbm_cyc_o : in std_logic; + mips_wbm_stb_o : in std_logic; + -- wishbone slave port(s) + -- ram_wbs + ram_wbs_dat_o : in std_logic_vector(31 downto 0); + ram_wbs_ack_o : in std_logic; + ram_wbs_dat_i : out std_logic_vector(31 downto 0); + ram_wbs_we_i : out std_logic; + ram_wbs_sel_i : out std_logic_vector(3 downto 0); + ram_wbs_adr_i : out std_logic_vector(31 downto 0); + ram_wbs_cyc_i : out std_logic; + ram_wbs_stb_i : out std_logic; + -- wbs + wbs_dat_o : in std_logic_vector(31 downto 0); + wbs_ack_o : in std_logic; + wbs_dat_i : out std_logic_vector(31 downto 0); + wbs_we_i : out std_logic; + wbs_sel_i : out std_logic_vector(3 downto 0); + wbs_adr_i : out std_logic_vector(31 downto 0); + wbs_cyc_i : out std_logic; + wbs_stb_i : out std_logic; + -- clock and reset + clk : in std_logic; + reset : in std_logic); + end intercon; + architecture rtl of intercon is - signal ram_wbs_ss : std_logic; -- slave select - signal wbs_ss : std_logic; -- slave select -begin -- rtl -decoder:block - signal adr : std_logic_vector(31 downto 0); -begin -adr <= (mips_wbm_adr_o); -ram_wbs_ss <= '1' when adr(31 downto 10)="0000000000000000000000" else -'0'; -wbs_ss <= '1' when adr(31 downto 10)="0000000000000000000001" else -'0'; -ram_wbs_adr_i <= adr(31 downto 0); -wbs_adr_i <= adr(31 downto 0); -end block decoder; - -mux: block - signal cyc, stb, we, ack : std_logic; - signal sel : std_logic_vector(3 downto 0); - signal dat_m2s, dat_s2m : std_logic_vector(31 downto 0); -begin -cyc <= (mips_wbm_cyc_o); -ram_wbs_cyc_i <= ram_wbs_ss and cyc; -wbs_cyc_i <= wbs_ss and cyc; -stb <= (mips_wbm_stb_o); -ram_wbs_stb_i <= stb; -wbs_stb_i <= stb; -we <= (mips_wbm_we_o); -ram_wbs_we_i <= we; -wbs_we_i <= we; -ack <= ram_wbs_ack_o or wbs_ack_o; -mips_wbm_ack_i <= ack; -sel <= (mips_wbm_sel_o); -ram_wbs_sel_i <= sel; -wbs_sel_i <= sel; -dat_m2s <= (mips_wbm_dat_o); -ram_wbs_dat_i <= dat_m2s; -wbs_dat_i <= dat_m2s; -dat_s2m <= (ram_wbs_dat_o and ram_wbs_ss) or (wbs_dat_o and wbs_ss); -mips_wbm_dat_i <= dat_s2m; -end block mux; - -end rtl; \ No newline at end of file + signal ram_wbs_ss : std_logic; -- slave select + signal wbs_ss : std_logic; -- slave select + begin -- rtl + decoder:block + signal adr : std_logic_vector(31 downto 0); + begin + adr <= (mips_wbm_adr_o); + ram_wbs_ss <= '1' when adr(31 downto 16)="0000000000000000" else '0'; + wbs_ss <= '1' when adr(31 downto 16)="0000000000000001" else '0'; + + ram_wbs_adr_i <= adr(31 downto 0); + wbs_adr_i <= adr(31 downto 0); + end block decoder; + + mux: block + signal cyc, stb, we, ack : std_logic; + signal sel : std_logic_vector(3 downto 0); + signal dat_m2s, dat_s2m : std_logic_vector(31 downto 0); + begin + cyc <= (mips_wbm_cyc_o); + ram_wbs_cyc_i <= ram_wbs_ss and cyc; + wbs_cyc_i <= wbs_ss and cyc; + stb <= (mips_wbm_stb_o); + ram_wbs_stb_i <= stb; + wbs_stb_i <= stb; + we <= (mips_wbm_we_o); + ram_wbs_we_i <= we; + wbs_we_i <= we; + ack <= ram_wbs_ack_o or wbs_ack_o; + mips_wbm_ack_i <= ack; + sel <= (mips_wbm_sel_o); + ram_wbs_sel_i <= sel; + wbs_sel_i <= sel; + dat_m2s <= (mips_wbm_dat_o); + ram_wbs_dat_i <= dat_m2s; + wbs_dat_i <= dat_m2s; + dat_s2m <= (ram_wbs_dat_o and ram_wbs_ss) or (wbs_dat_o and wbs_ss); + mips_wbm_dat_i <= dat_s2m; + end block mux; + end rtl; \ No newline at end of file diff --git a/sw/Makefile b/sw/Makefile index 2207685..3191ebe 100644 --- a/sw/Makefile +++ b/sw/Makefile @@ -1,22 +1,23 @@ CFLAGS = -O2 -Wall -c -s -GCC_MIPS = mips-sde-elf-gcc $(CFLAGS) -AS_MIPS = mips-sde-elf-as -LD_MIPS = mips-sde-elf-ld -DUMP_MIPS = mips-sde-elf-objdump -COPY_MIPS = mips-sde-elf-objcopy -CONVERT = cat test.vh | perl -pe 's/([\dA-F]{2})\s+([\dA-F]{2})\s+([\dA-F]{2})\s+([\dA-F]{2})/$$1$$2$$3$$4/g;' > test.rom - +GCC_MIPS = mips-sde-elf-gcc $(CFLAGS) +AS_MIPS = mips-sde-elf-as +LD_MIPS = mips-sde-elf-ld +DUMP_MIPS = mips-sde-elf-objdump +COPY_MIPS = mips-sde-elf-objcopy +CONVERT_TEXT = cat text.vh | perl -pe 's/([\dA-F]{2})\s+([\dA-F]{2})\s+([\dA-F]{2})\s+([\dA-F]{2})/$$1$$2$$3$$4/g;' > text.rom +CONVERT_DATA = cat data.vh | perl -pe 's/([\dA-F]{2})\s+([\dA-F]{2})\s+([\dA-F]{2})\s+([\dA-F]{2})/$$1$$2$$3$$4/g;' > data.rom LIBS = - all: $(AS_MIPS) -o test.o test.asm - $(LD_MIPS) -Ttext 0x0 -Tdata 0x200 -eentry -o test.axf test.o + $(LD_MIPS) -Ttext 0x0 -Tdata 0x1000 -eentry -o test.axf test.o $(DUMP_MIPS) --disassemble test.axf > test.lst - $(COPY_MIPS) -O verilog test.axf test.vh - $(CONVERT) + $(COPY_MIPS) -O verilog -R .text test.axf data.vh + $(COPY_MIPS) -O verilog -R .data test.axf text.vh + $(CONVERT_TEXT) + $(CONVERT_DATA) clean: rm -f *.o diff --git a/sw/test.asm b/sw/test.asm index 496cf37..3890cf9 100644 --- a/sw/test.asm +++ b/sw/test.asm @@ -7,12 +7,12 @@ .text /* code goes to text section*/ .ent entry entry: - lw $t0, 0x200 /* t0 = 1*/ - sw $t0, 0x202 - lw $t1, 0x201 /* t1 = 1*/ - lw $t1, 0x200 /* t0 = 1*/ + lw $t0, 0x1000 /* t0 = 1*/ + sw $t0, 0x1002 + lw $t1, 0x1001 /* t1 = 1*/ + lw $t1, 0x1000 /* t0 = 1*/ add $t0, $t0, $t1 /* t0 = t0 + t1 = 2*/ - sw $t0, 0x400 + sw $t0, 0x1200 add $t0, $t0, 0xB /* t0 = t0 + 0xB == 0xD*/ sub $t0, $t0, $t1 /* t0 = t0 - $t1 == 0xC*/ or $t0, $t0, 0x10 /* t0 = t0 | 0x10 == 0x1C*/ -- cgit v1.1