1 files changed, 90 insertions, 0 deletions
diff --git a/hdl/wb_slave_ctrl_testbench.v b/hdl/wb_slave_ctrl_testbench.v
new file mode 100644
index 0000000..36640fd
--- /dev/null
+++ b/hdl/wb_slave_ctrl_testbench.v
@@ -0,0 +1,90 @@
+`timescale 1ns / 1ps
+
+module wb_slave_ctrl_testbench;
+
+	// Inputs
+	reg wb_clk_i;
+	reg wb_rst_i;
+	reg [31:0] wb_dat_i;
+	reg [4:0] wb_adr_i;
+	reg wb_we_i;
+	reg [3:0] wb_sel_i;
+	reg wb_cyc_i;
+	reg wb_stb_i;
+	reg [7:0] data_i;
+	reg [7:0] step_i;
+
+	// Outputs
+	wire [31:0] wb_dat_o;
+	wire wb_ack_o;
+	wire [7:0] data_o;
+	wire [7:0] step_o;
+	wire data_val_o;
+	wire step_val_o;
+
+	// Instantiate the Unit Under Test (UUT)
+	wb_slave_ctrl uut (
+		.wb_clk_i(wb_clk_i),
+		.wb_rst_i(wb_rst_i),
+		.wb_dat_i(wb_dat_i),
+		.wb_adr_i(wb_adr_i),
+		.wb_we_i(wb_we_i),
+		.wb_sel_i(wb_sel_i),
+		.wb_cyc_i(wb_cyc_i),
+		.wb_stb_i(wb_stb_i),
+		.wb_dat_o(wb_dat_o),
+		.wb_ack_o(wb_ack_o),
+		.data_o(data_o),
+		.step_o(step_o),
+		.data_val_o(data_val_o),
+		.step_val_o(step_val_o),
+		.data_i(data_i),
+		.step_i(step_i)
+	);
+
+	initial begin
+	  forever begin
+	    wb_clk_i = ~wb_clk_i;
+		 #100;
+	  end
+	end
+
+
+	initial begin
+		// Initialize Inputs
+		wb_clk_i = 0;
+		wb_rst_i = 0;
+		wb_dat_i = 0;
+		wb_adr_i = 0;
+		wb_we_i = 0;
+		wb_sel_i = 0;
+		wb_cyc_i = 0;
+		wb_stb_i = 0;
+		data_i = 0;
+		step_i = 0;
+
+		// Wait 100 ns for global reset to finish
+		#100;
+
+		wb_rst_i = 1;
+		#100;
+		wb_rst_i = 0;
+
+		#100;
+		data_i = 8'b00001111;
+		step_i = 8'b00001010;
+	   wb_cyc_i = 1;
+		wb_stb_i = 1;
+		wb_we_i  = 0;
+		wb_adr_i = 1;
+
+		#100;
+		#100;
+		#100;
+
+		wb_cyc_i = 0;
+		wb_stb_i = 0;
+	end
+
+endmodule
+