1 files changed, 76 insertions, 0 deletions
diff --git a/hdl/wb_slave_ctrl.v b/hdl/wb_slave_ctrl.v
new file mode 100644
index 0000000..95e5d18
--- /dev/null
+++ b/hdl/wb_slave_ctrl.v
@@ -0,0 +1,76 @@
+`timescale 1ns / 1ps
+
+module wb_slave_ctrl #(parameter BASE_ADDR = 32'h00000400)(
+  input wb_clk_i,
+  input wb_rst_i,
+  input [31:0] wb_dat_i,
+  input [31:0] wb_adr_i,
+  input wb_we_i,
+  input [3:0] wb_sel_i,
+  input wb_cyc_i,
+  input wb_stb_i,
+
+  output reg [31:0] wb_dat_o,
+  output wb_ack_o,
+
+  output reg[7:0] data_o,
+  output reg[7:0] step_o,
+  output reg data_val_o,
+  output reg step_val_o,
+
+  input [7:0] data_i,
+  input [7:0] step_i
+);
+
+  localparam REG_DATA = BASE_ADDR + 0;
+  localparam REG_STEP = BASE_ADDR + 1;
+
+  reg dat_ready = 0;
+
+  assign read_i  = wb_cyc_i & wb_stb_i & !wb_we_i;
+  assign write_i = wb_cyc_i & wb_stb_i & wb_we_i;
+
+  assign wb_ack_o = (wb_cyc_i && wb_stb_i) && (data_val_o || step_val_o || dat_ready);
+
+  always @(posedge wb_clk_i)
+    if( write_i && wb_adr_i == REG_DATA )
+	   begin
+		  data_o <= wb_dat_i;
+		  data_val_o <= 1;
+		end
+	 else
+	   begin
+		  data_o <= 0;
+		  data_val_o <= 0;
+		end
+
+    always @(posedge wb_clk_i)
+      if( write_i && wb_adr_i == REG_STEP )
+	     begin
+		    step_o <= wb_dat_i;
+		    step_val_o <= 1;
+		  end
+	   else
+	     begin
+		    step_o <= 0;
+		    step_val_o <= 0;
+		  end
+
+  always @(posedge wb_clk_i)
+    if( read_i && wb_adr_i == REG_DATA )
+	   begin
+		  wb_dat_o <= data_i;
+		  dat_ready <= 1;
+		end
+	 else if( read_i && wb_adr_i == REG_STEP )
+	   begin
+	     wb_dat_o <= step_i;
+        dat_ready <= 1;
+		end
+    else
+	   begin
+		  wb_dat_o <= 0;
+		  dat_ready <= 0;
+		end
+
+endmodule