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authorSnuffick <aleks.bae@gmail.com>2015-12-04 14:13:04 +0300
committerSnuffick <aleks.bae@gmail.com>2015-12-04 14:13:04 +0300
commit49f076385c73b738acb508c3806678f058d4ceb6 (patch)
tree9a32834291778a576494c5570b660a6bfa7f8597 /hdl
parentdc61e35246cfa66df78be782f9514f421db4bb9d (diff)
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Исправлена ошибка, приводящая к невозможности синтеза проекта (файл hazard_unit.v).
Файл test.asm был скорректирован (код теперь соответствует комментариям). Был добавлен скрипт convert.py, генерирующий файлы инициализации для памяти. Для сборки спомощью makefile теперь необходимо установить python версии 2.7+ (наличие perl больше не требуется)
Diffstat (limited to 'hdl')
-rw-r--r--hdl/dp_memory.v2
-rw-r--r--hdl/hazard_unit.v15
-rwxr-xr-xhdl/ram_wb/wb_ram_sc_sw.v10
-rw-r--r--hdl/testbench.v2
4 files changed, 16 insertions, 13 deletions
diff --git a/hdl/dp_memory.v b/hdl/dp_memory.v
index 9db03c3..e1fe991 100644
--- a/hdl/dp_memory.v
+++ b/hdl/dp_memory.v
@@ -44,7 +44,7 @@ module bus_control #(
reg [31:0] memory[addr_low:addr_high];
- initial begin
+ initial begin
$readmemh("text.rom", memory, addr_low, addr_high);
end
diff --git a/hdl/hazard_unit.v b/hdl/hazard_unit.v
index 2af5896..83531e7 100644
--- a/hdl/hazard_unit.v
+++ b/hdl/hazard_unit.v
@@ -37,14 +37,15 @@ module hazard_unit( input clk, // isn't needed for now
assign pstop_o = mem_wait_r;
- always@(posedge clk, posedge rst)
- if(rst || wb_done_i) begin
+ always@(posedge clk, posedge rst) begin
+ if(rst)
mem_wait_r = 0;
- end else begin
- if (id_opcode == LW || id_opcode == SW)
- mem_wait_r = (id_opcode == LW || id_opcode == SW);
- end
-
+ else if (wb_done_i)
+ mem_wait_r = 0;
+ else if (id_opcode == LW || id_opcode == SW)
+ mem_wait_r = (id_opcode == LW || id_opcode == SW);
+ end
+
reg [1:0] coincidence;
always @* begin
diff --git a/hdl/ram_wb/wb_ram_sc_sw.v b/hdl/ram_wb/wb_ram_sc_sw.v
index cfc807a..6d487a7 100755
--- a/hdl/ram_wb/wb_ram_sc_sw.v
+++ b/hdl/ram_wb/wb_ram_sc_sw.v
@@ -8,18 +8,20 @@ module ram #(
input wren_i,
output reg [31:0] data_o,
input clk_i);
+
+ wire [31:0] addr_real = addr_i - addr_low;
- reg [31:0] memory [addr_low:addr_high] /* synthesis ram_style = no_rw_check */;
+ reg [31:0] memory [0:addr_high - addr_low] /* synthesis ram_style = no_rw_check */;
initial begin
- $readmemh("data.rom", memory, addr_low, addr_high);
+ $readmemh("data.rom", memory, 0, addr_high - addr_low);
end
always @ (posedge clk_i) begin
- data_o <= memory[addr_i];
+ data_o <= memory[addr_real];
if (wren_i && !read_only)
- memory[addr_i] <= data_i;
+ memory[addr_real] <= data_i;
end
endmodule // ram
diff --git a/hdl/testbench.v b/hdl/testbench.v
index cde4467..fc9d23e 100644
--- a/hdl/testbench.v
+++ b/hdl/testbench.v
@@ -36,7 +36,7 @@ module testbench;
integer i;
initial begin
- for (i = 0; i < 1000; i=i+1)
+ for (i = 0; i < 100000000; i=i+1)
@(posedge mips_clk);
$stop();