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| author | Snuffick <aleks.bae@gmail.com> | 2015-09-21 14:52:33 +0300 |
|---|---|---|
| committer | Snuffick <aleks.bae@gmail.com> | 2015-09-21 14:52:33 +0300 |
| commit | 3b6c45c55262fb5ad6a6eaff05e89d0faef47341 (patch) | |
| tree | d9784a4ee337ef15c3a7e3822437712bc1deb1cf /hdl/wb_stage.v | |
| parent | b3d9beada656bce070e8aeb2d74a859a29a54b56 (diff) | |
| download | MIPSLabs-3b6c45c55262fb5ad6a6eaff05e89d0faef47341.zip MIPSLabs-3b6c45c55262fb5ad6a6eaff05e89d0faef47341.tar.gz MIPSLabs-3b6c45c55262fb5ad6a6eaff05e89d0faef47341.tar.bz2 | |
Отредактировал исходники
Diffstat (limited to 'hdl/wb_stage.v')
| -rw-r--r-- | hdl/wb_stage.v | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/hdl/wb_stage.v b/hdl/wb_stage.v index 37cfc38..66ff2a9 100644 --- a/hdl/wb_stage.v +++ b/hdl/wb_stage.v @@ -1,11 +1,9 @@ `timescale 1ns / 1ps -module wb_stage( - input mem_to_reg, - input [31:0] mem_out, alu_out, - output [31:0] write_data - ); +module wb_stage( input mem_to_reg, + input [31:0] mem_out, alu_out, + output [31:0] write_data ); - assign write_data = mem_to_reg ? mem_out : alu_out; + assign write_data = mem_to_reg ? mem_out : alu_out; endmodule |