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authorSnuffick <aleks.bae@gmail.com>2015-09-21 14:52:33 +0300
committerSnuffick <aleks.bae@gmail.com>2015-09-21 14:52:33 +0300
commit3b6c45c55262fb5ad6a6eaff05e89d0faef47341 (patch)
treed9784a4ee337ef15c3a7e3822437712bc1deb1cf /hdl/testbench.v
parentb3d9beada656bce070e8aeb2d74a859a29a54b56 (diff)
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Отредактировал исходники
Diffstat (limited to 'hdl/testbench.v')
-rw-r--r--hdl/testbench.v116
1 files changed, 56 insertions, 60 deletions
diff --git a/hdl/testbench.v b/hdl/testbench.v
index 6100226..a980d65 100644
--- a/hdl/testbench.v
+++ b/hdl/testbench.v
@@ -2,72 +2,68 @@
module testbench;
-
- // Inputs
- reg clk;
- reg rst;
- reg [31:0] ext_data_in;
-
- // Outputs
- wire ext_write_en;
- wire ext_read_en;
- wire [31:0] ext_addr;
- wire [31:0] ext_write_data;
-
- // Instantiate the Unit Under Test (UUT)
- mips_system uut (
- .clk(clk),
- .rst(rst),
- .ext_write_en(ext_write_en),
- .ext_read_en(ext_read_en),
- .ext_addr(ext_addr),
- .ext_write_data(ext_write_data),
- .ext_data_in(ext_data_in)
- );
-
- initial begin
- rst = 1;
- ext_data_in = 0;
+
+ //Inputs
+ reg mips_clk;
+ reg mips_rst;
+
+ //Outputs
+ wire mem_instr_read;
+ wire [31:0] mem_instr_addr_bus, mem_instr_read_bus;
+
+ wire mem_data_write, mem_data_read;
+ wire [31:0] mem_data_addr_bus, mem_data_read_bus, mem_data_write_bus;
+
+ //Instantiate the Unit Under Test (UUT)
+ mips_system uut (
+ .clk(mips_clk),
+ .rst(mips_rst),
+
+ .mem_instr_read(mem_instr_read),
+ .mem_instr_addr_bus(mem_instr_addr_bus),
+ .mem_instr_read_bus(mem_instr_read_bus),
+
+ .mem_data_write(mem_data_write),
+ .mem_data_read(mem_data_read),
+ .mem_data_addr_bus(mem_data_addr_bus),
+ .mem_data_read_bus(mem_data_read_bus),
+ .mem_data_write_bus(mem_data_write_bus));
+
+ initial begin
+ mips_rst = 1;
+
+ // Wait 100 ns for global reset to finish
+ #100;
+ mips_rst = 0;
- // Wait 100 ns for global reset to finish
- #100;
- rst = 0;
-
- end // initial begin
-
-
- initial begin
- clk = 0;
- forever
- #10 clk = !clk;
- end
-
-
+ end // initial begin
+
+ initial begin
+ mips_clk = 0;
+ forever
+ #10 mips_clk = !mips_clk;
+ end
+
integer i;
- initial begin
-
- for (i = 0; i < 1000; i=i+1)
- @(posedge clk);
-
+
+ initial begin
+ for (i = 0; i < 1000; i=i+1)
+ @(posedge mips_clk);
- $stop();
- end
+ $stop();
+ end
- initial
- begin
- $display("Trace register $t0");
- @(negedge rst);
+ initial begin
+ $display("Trace register $t0");
+
+ @(negedge mips_rst);
- forever
- begin
- @(posedge clk);
- $display("$t0 (REG8) = %x",uut.pipeline_inst.idecode_inst.regfile_inst.rf[8]);
- end
+ forever begin
+ @(posedge mips_clk);
-
-
- end
-
+ $display("%d ns: $t0 (REG8) = %x", $time, uut.pipeline_inst.idecode_inst.regfile_inst.rf[8]);
+ end
+ end
endmodule