Исправлена ошибка, приводящая к невозможности синтеза проекта (файл hazard_unit.v).

Файл test.asm был скорректирован (код теперь соответствует комментариям).

Был добавлен скрипт convert.py, генерирующий файлы инициализации для памяти.

Для сборки спомощью makefile теперь необходимо установить python версии 2.7+ (наличие perl больше не требуется)

7 files changed, 107 insertions, 27 deletions

diff --git a/hdl/dp_memory.v b/hdl/dp_memory.v
index 9db03c3..e1fe991 100644
--- a/hdl/dp_memory.v
+++ b/hdl/dp_memory.v
@@ -44,7 +44,7 @@ module bus_control #(
           
      reg [31:0] memory[addr_low:addr_high];
      
-     initial begin
+     initial begin     
           $readmemh("text.rom", memory, addr_low, addr_high);      
      end
      
diff --git a/hdl/hazard_unit.v b/hdl/hazard_unit.v
index 2af5896..83531e7 100644
--- a/hdl/hazard_unit.v
+++ b/hdl/hazard_unit.v
@@ -37,14 +37,15 @@ module hazard_unit( input       clk,       //     isn't needed for now
      
      assign pstop_o = mem_wait_r;
      
-     always@(posedge clk, posedge rst)
-        if(rst || wb_done_i) begin 
+     always@(posedge clk, posedge rst) begin
+        if(rst)  
             mem_wait_r = 0;
-        end else begin
-            if (id_opcode == LW || id_opcode == SW)
-                mem_wait_r = (id_opcode == LW || id_opcode == SW);
-        end
-
+        else if (wb_done_i)
+            mem_wait_r = 0;
+        else if (id_opcode == LW || id_opcode == SW)
+            mem_wait_r = (id_opcode == LW || id_opcode == SW);
+     end
+     
      reg [1:0] coincidence;
    
      always @* begin
diff --git a/hdl/ram_wb/wb_ram_sc_sw.v b/hdl/ram_wb/wb_ram_sc_sw.v
index cfc807a..6d487a7 100755
--- a/hdl/ram_wb/wb_ram_sc_sw.v
+++ b/hdl/ram_wb/wb_ram_sc_sw.v
@@ -8,18 +8,20 @@ module ram #(
      input             wren_i,
      output reg [31:0] data_o,
      input             clk_i);    
+     
+     wire [31:0] addr_real = addr_i - addr_low;
    
-     reg [31:0] memory [addr_low:addr_high] /* synthesis ram_style = no_rw_check */;
+     reg [31:0] memory [0:addr_high - addr_low] /* synthesis ram_style = no_rw_check */;
       
      initial begin
-          $readmemh("data.rom", memory, addr_low, addr_high);      
+          $readmemh("data.rom", memory, 0, addr_high - addr_low);      
      end
       
      always @ (posedge clk_i) begin 
-          data_o <= memory[addr_i];
+          data_o <= memory[addr_real];
           
           if (wren_i && !read_only)
-               memory[addr_i] <= data_i;
+               memory[addr_real] <= data_i;
      end 
 
 endmodule // ram
diff --git a/hdl/testbench.v b/hdl/testbench.v
index cde4467..fc9d23e 100644
--- a/hdl/testbench.v
+++ b/hdl/testbench.v
@@ -36,7 +36,7 @@ module testbench;
 	integer i;
      
      initial begin
-          for (i = 0; i < 1000; i=i+1)
+          for (i = 0; i < 100000000; i=i+1)
                @(posedge mips_clk);
 
           $stop();      
diff --git a/sw/Makefile b/sw/Makefile
index 0c8b0db..0e3580e 100644
--- a/sw/Makefile
+++ b/sw/Makefile
@@ -1,12 +1,11 @@
 CFLAGS =	-O2 -Wall -c -s 
 
-GCC_MIPS     = mips-sde-elf-gcc $(CFLAGS)
-AS_MIPS      = mips-sde-elf-as
-LD_MIPS      = mips-sde-elf-ld
-DUMP_MIPS    = mips-sde-elf-objdump
-COPY_MIPS    = mips-sde-elf-objcopy
-CONVERT_TEXT = cat text.vh | perl -pe 's/([\dA-F]{2})\s+([\dA-F]{2})\s+([\dA-F]{2})\s+([\dA-F]{2})/$$1$$2$$3$$4/g;' > text.rom
-CONVERT_DATA = cat data.vh | perl -pe 's/([\dA-F]{2})\s+([\dA-F]{2})\s+([\dA-F]{2})\s+([\dA-F]{2})/$$1$$2$$3$$4/g;' > data.rom
+GCC_MIPS       = mips-sde-elf-gcc $(CFLAGS)
+AS_MIPS        = mips-sde-elf-as
+LD_MIPS        = mips-sde-elf-ld
+DUMP_MIPS      = mips-sde-elf-objdump
+COPY_MIPS      = mips-sde-elf-objcopy
+CONVERT        = python convert.py 512 1024
 
 LIBS =
 
@@ -16,8 +15,7 @@ all:
 	$(DUMP_MIPS) --disassemble test.axf > test.lst
 	$(COPY_MIPS) -O verilog -R .text test.axf data.vh
 	$(COPY_MIPS) -O verilog -R .data test.axf text.vh
-	$(CONVERT_TEXT)
-	$(CONVERT_DATA)
+	$(CONVERT)
 
 clean:
 	rm -f *.o
diff --git a/sw/convert.py b/sw/convert.py
new file mode 100644
index 0000000..c96b83c
--- /dev/null
+++ b/sw/convert.py
@@ -0,0 +1,82 @@
+# -*- coding: utf-8 -*-
+"""
+Created on Fri Dec 04 13:10:20 2015
+
+@author: bayevskihk
+"""
+
+import sys
+
+def main(argv):
+    number    = len(argv)
+    data_addr = 0
+    last_addr = 0 
+    
+    if(number != 2):
+        return
+    else:
+        try:
+            data_addr = int(argv[0])
+            last_addr = int(argv[1])
+        except:
+            print "Wrong arguments"
+            return
+        
+        if(parse("text.vh", "text.rom", data_addr) < 0):
+            print "Wrong text file"
+            return
+            
+        if(parse("data.vh", "data.rom", last_addr - data_addr) < 0):
+            print "Wrong text file"
+            return
+        
+        print "Convertion was successfull"
+        
+        
+def parse(file_name, rom_name, addr_last):
+    hex_file = open(file_name, 'r')
+    rom_file = open(rom_name, 'w')  
+    rom_file.truncate()
+    
+    hex_parts = hex_file.readline()
+    
+    try:
+        hex_parts.index("@")
+    except:
+        return -1
+        
+    attached = 0
+    words = 0    
+    
+    rom_file.writelines("@00000000\n");
+        
+    while(1):        
+        hex_parts = hex_file.readline()    
+        hex_parts = hex_parts.split(" ");
+        
+        if(len(hex_parts) == 1):
+            break
+        
+        for part in hex_parts:
+            
+            if(part == "\n"):
+                continue            
+            
+            rom_file.write(part)
+            attached += 1
+            
+            if(attached == 4):
+                attached = 0    
+                words += 1
+                rom_file.write("\n")
+    
+    for i in range(addr_last - words):
+        rom_file.write("00000000\n")
+    
+    rom_file.close()
+    
+    return 0
+
+if __name__ == '__main__':
+    main(sys.argv[1:])
+    
\ No newline at end of file
diff --git a/sw/test.asm b/sw/test.asm
index 63ce753..eac3c7e 100644
--- a/sw/test.asm
+++ b/sw/test.asm
@@ -8,11 +8,8 @@
 .ent entry
 entry:
 	    lw $t0, 0x200        /* t0 = 1*/
-	    sw $t0, 0x400
-        lw $t1, 0x201        /* t1 = 1*/
-	    lw $t1, 0x200        /* t0 = 1*/
-        add $t0, $t0, $t1     /* t0 = t0 + t1 = 2*/ 
-        sw $t0, 0x400
+	    lw $t1, 0x201        /* t1 = 1*/
+	    add $t0, $t0, $t1     /* t0 = t0 + t1 = 2*/ 
         add $t0, $t0, 0xB     /* t0 = t0 + 0xB  == 0xD*/
         sub $t0, $t0, $t1     /* t0 = t0 - $t1  == 0xC*/
         or $t0, $t0, 0x10     /* t0 = t0 | 0x10 == 0x1C*/